The read/restore mode of memory operation retrieves data previously stored in a memory location and re-stores the same data back in the addressed memory location. The read/restore mode is initiated when a user device has been granted access to memory and the read {store) mode is specified by the device.
The read/write or store signal from the user de-vice is applied to the memory control unit where GOMRRQ is enabled and GOMWRQ is disabled for the
read/restore mode. GOMRRQ enables the parity check function of the parity check-generate logic.
GOMWRQ applies a "one" to the memory unit enabling the read cycle enable gate DlTRRE. DlTRRE enables the data sensed from core to be gated to the memory data register for transfer to the user device and for control of the bit drive lines during the write portion of the memory cycle.
Fig. THEORY. 13 mustrates the data flow for the read/restore memory operation. During the read portion of the memory cycle, the bit and word drive lines are enabled according to the memory address specified by the user device. These drive lines pro-vide full select current to flip the addressed core cells that are in the "one" state to the "zero" state.
Flipping these cores to the "zero" state induces a voltage into the sense lines. The sense quad enable
·signal {DlTSQ ) is enabled corresponding to the 4K plane addressed. This sense quad enable signal gates the sense winding signal for each bit through the sense amplifiers. The sense amplifiers convert the sense winding signals to logic levels. From the sense amplifiers, the data read from core is gated into the memory data register since this is a read/
restore operation {i.e., DlTRRE is enabled).
The data contained by the memory data register is then used to control the bit drive lines during the write portion of the memory cycle to restore the contents of the memory location addressed. Bits 23 through 0 of the memory data register are also tr an sf erred to signal generated within the memory control unit is applied to the user device to gate the data to the B Register (GOBP23-00) if the AU is the user or to the data register of the Bulk Memory Controller, channel 1 or 2 user. Bit 24 of the memory data register is applied to the parity check circuitry of the memory control unit.
The data gated to the user is applied back through the multiplexer (or direct from the B Register in systems not requiring the multiplexer) to the parity check logic. In this manner, transmission parity is also checked. A detailed discussion of parity checking is provided later in this section.
As mentioned above, the data in the memory data register is used to control the bit drive lines during the write portion of the memory cycle. If a "one" is to be stored into a core cell, full select current is passed through the cell in a direction opposite to that of the read portion of the cycle. If the core is to re-main in the "zero" state, no current flows in the bit drive lines, only one-half select current flows through the core from the word drive lines, and the core remains in the "zero" state.
4016B/5174-T CORE MEMORY THEORY-13
WRITE Bit
Group Drive
READ
READ Bit
Diode Drive
WRITE
WRITE Bit
Group Drive
READ
WRITE Bit
Diode Drive
READ
11: 12
0 ii 0 10 0 0 9 8 0 7 0 6 0 5 0 4 0 0 3 2 0 0~
ADDRESS REGISTER
Word Diode Drive
(
READ
,,,,,....__
LOWDOO
r -GOBOXX
I
GlBOXX
I L-
- -
-DOBOXX
DlBOXX READ I
i
r - -
-
-GlBOOl
GOBOOl
L _
- -
-DOBOXX
DlBOXX
LOW GOO
WRITE
WRITE "\
LlWDOO
-
- - - -1
WRITE I I
._____
Even Numbered Bits of Memory Location
.__
000008 .READ I I
- - _ _ _ _ _ J
l
-WRITE I
- - - ,
WRITE I
----+
Odd Numbered Bits of Memory Location----+
I000008.
READ I I
- - - - _j
LlWGOO }
Word Group Drive READ
Fig. THEORY. 10 Address Selection Block Diagram
13 12 11 10 9 8 7 6 5 4 3 2 0 Address Register
= I
0 0 0 0 0 0 0 0 0 0 0 0 0 00 = Word Read Drive • Lower Word Switch Enable
SlWLRD Sheet 13 +1. 6V
SlWLRE = Lower Word Read Drive
BLM ,~,+5V AR
LOWDRS Sheet 17
Sheet 21
LOWDXO
LOWD OX Sheet 14
LOWDlO LOWDOO
LlWDlO LlWDOO
Sheet 17 Sheet 11 SlBROO
(
GOBOOO +(Enabled During
Read By TESL) GlBOOO
i
I-12VL GlBAXO
GlBMXO Sheet 10. 1
1.6VM
+12VM Sheet 11
SlBROO
t
I(Enabled During DOBOOO Read By TBSL)
AR2 • AR
3 ·Read -12VL
DO BM OX
1.6VM Sheet 11 Sheet 17
LOWGlO LOWGOO
+
Sheet 13 LlWGlO LlWGOO.
Read·AR 4·AR
5 +
LlWGXO
-AR6 • AR
7 LOWGOX
Sheet 13
Fig. THEORY. 11 Read Drive Circuit
4016B/5174-T CORE MEMORY THEORY-15
13 12 11 10 9 8 7 6 5 4 3 2 0 Address Register =
I
0 0 0 0 0 0 0 0 0 0 0 0 0 00
=
Word Write Drive · Lower Word Switch EnableSlWLWD Sheet 13
BLM "C" +5V
1. 6V
1
=
Lower Word Write Drive SlWLWELlWDWS
Sheet 21 Sheet 17
Sheet 17
LOWDlO LOWDOO
+
LlWDlO LlWDOO
Sheet 14
Sheet 14
l
Word WriteAR10· AR11 • AR12
LOWDOX
ARo· AR 1. AR 3 • Write GOBAXO
GOBMXO
-12VL
Data ( Bit = 1 Enable +12VM
Sheet 11 Sheet 11
DlBAOX
r
WriteI Bit
+1. 6VM -12VL
+12VM LOWGXO
Sheet 13 LOWGlO LOW GOO
AR6·AR
7 LOWGOX LlWGlO LlWGOO
Sheet 13 Sheet 17
Fig. THEORY. 12. Write Drive Circuit
CORE STACK
- - - - Write Word Drive Line
CORE STACK
Read Bit Drive Line Read Word Drive Line
-Sense Quad (DlTSQ_)
Read/Restore (DlTRRE)
GODS(XX) XX
=
Bit Position 00-24MEMORY MODULE (70C180023)
MEMORY CONTROL (70Cl80872)
24 0
MEMORY DATA REGISTER.
Used On Systems With More Than 16K And Either Channel 1 or Channel 2 Implemented
DR24
GO DR XX
---M S U - - - . GlMPBT
PARITY CHECK
MB23
MEMORY INPUT BUFFER
GlDRXX
MBOO
23 0
USER DEVICE USER DEVICE I/0 DAT A REGISTER
Fig. THEORY. 13 Read/Restore Block Diagram
4016B/5174-T CORE MEMORY
BIT DRIVE
Used On Systems With 16K and Channel 2 or 3 Not Implemented
THEORY-17