Fig. THEORY. 8 illustrates the timing of the memory module. Because of the operational speed of the mem-ory unit, circuit delays become important when consid-ering the memory timing. These delays are taken in-to account in the timing diagram.
These signals are generated from the initiate signal (G1MIS1(2) generated in the memory control unit
The timing pulse applied to the delay circuits provide precise timing signals for control during the memory cycle. Three delay circuits are provided as shown on sheet 8 of the memory logic {70C180023). Delay circuits 1 (DLl) and 2 (DL2) provide taps for obtaining delays of the timing pulse from 25 nanoseconds to 1650 nanoseconds in 25 nanosecond intervals. Delay circuit 3 (DL3) is used to generate the strobe pulse providing more precise delay increments of 5 nano-seconds from the timing pulse previously delayed in delay circuit 1.
The timing signals obtained from these delay circuits are wired to the delay tap pins to provide 'optimum operation of the memory module. These delays should not require changing unless component deterio-ration or component replacement occurs.
Each of the control signals illustrated in Fig.
THEORY. 8 are described as to the function performed in the following text. A more detailed understanding of these signals will be obtained from the discussion of memory addressing, and the read/restore and clear /write modes of memory operation contained later in this section.
G1MIS1(2) - Initiate:
The initiate signal originates in the memory con-trol unit when access has been granted to a re-questing device. This signal is applied from GlMISl to the first 16K stack of memory storage.
If the system contains more than 16K words of memory, the initiate signal is applied from G1MIS2 to the upper 16K stack. In systems with more than 16K words of storage, the initiate signal is applied only to the addressed 16K mem-ory module.
This initiate signal is used to start the memory timing by applying a pulse to the delay circuits from which the remaining timing signals are ob-tained.
DlTGAB - Gate Address, Bit:
This signal gates address bits 3 through 0 from memory control to the address register (F1AR03-F1AROO) of the memory module. These bits are decoded to select the bit drive lines.
At the same time that DlTGAB is enabled, DlTGAL and DlTGAU are enabled to gate address bits 4 through 12 to the lower and upper 8K memory address register, respectively, of the memory module. These bits are decoded to
select the word drive lines. Dl TGAL is also used to gate address bits 12 and 13 to the mem-ory address register from the memmem-ory control unit. These bits are decoded to select the sense quad enable signal (DlTSQ0-3) corresponding to the 4K plane addressed.
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Fig. THEORY. 7 AU/Memory Cycle Relationship
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Fig. THEORY. 8 Memory TimingFOTBRE - Bit Read Enable: addressed bit drive line of the read portion of the memory cycle.
GOTWSL - Word Switch Enable:
GOTWSL supplies one input to enable decoding of address bits 12 through 4 for selection of the addressed word drive lines. The other enable signal required for selecting the word drive lines is the word read enable or word write enable
Fl TWRD enables the voltage source for the word drive lines. Therefore, current will flow through the addressed word drive lines. In conjunction with the current flow through the bit drive lines, full select current will flow through the addressed word and the core will be flipped to the zero state.
DlTSQ0-3 Sense Quad Enable:
This signal enables the sense amplifier to detect the change in flux for a core cell flipped from the data register during a clear /write operation.
The data gated to the memory data register will be the data from the user device that is multiplexed through the memory control unit.
DI TBSL - Bit Switch Enable:
DlTBSL gates the contents of the memory data register to the bit matrix for controlling the bit drive lines during the write or restore portion of the memory cycle. Only the addressed bit lines corresponding to one bits in the memory data register will be enabled. This will flip the addressed cores corresponding to ones in the memory data register and leave the remaining cores in the zero state.
FOTBWT - Bit Write Enable~
FOTBWT enables the decoding of address bits 3 through 0 for selection of the bit drive lines for the write portion of the memory cycle.
FOTWWE - Word Write Enable·
FOTWWE enables decoding of address bits 12 through 0 for selection of the word drive lines for the write or restore portion of the memory cycle.
FlTWWD - Word Write Drive:
This signal enables the voltage source for the selected word drive lines and, therefore, allows current to flow through these lines. Therefore, with current flowing in the word drive lines and in the bit drive lines for those cells in which a one is to be stored, full select current flows, flipping them to the one state.
Fl TMBU - Memory Busy:
This signal inhibits initiation of a memory cycle until the present cycle is completed. In this manner, protection is provided from destroying desired data.
Current Signals:
These signals are provided to illustrate the current waveforms on the drive line.