The following dlscussion describes the functional block diagram of the 4022D Arithmetic Unit. Fig.
DESC. 1 contains a block diagram of the Arithmetic Unit illustrating the interconnection of the various registers, parallel adder unit, serial adder, and the associated core memory module. This diagram does not attempt to define timing, sequencing, or control organization.
A Register (Accumulator)
The A Register is the accumulator for arithmetic and bit manipulation operation and temporary storage for data coming from or going to the registers of the I/O equipment. It is comprised of 24 high-speed flip-fl.ops in a bit configuration numbered 00-23 with bit right where the contents of A
0 enter either B programming and maintenance console.
B Register {Buffer}
The B Register is a 24- bit register used to hold all instructions and AU data going to or coming from core memory. During the fetch portion of an in-struction, the 10 most significant bits of the B Regi-ster are transferred in parrallel to the I RegiRegi-ster for decoding. The contents of the B Register are routed in parallel to the Parallel Full Adder in two fields: B13-0 for address modification, and B23-0 for full register operations. The contents of the Parallel Full Adder may be routed to the B Register in parallel.
The B Register may act as an extension to the A Register when performing right and left shifts (MPY, DVD, GEN 3, TIM/fOM). During a left shift, the contents of either B
23 or B and mainenance console.
P Register (Program}
The P Register is a 15-bit binary counter register whose primary function is to control the addressing of the next instruction. Depending upon the instruction being executed, the P Register may be incremented by one or two. Information from the I Register (address) is transferred to the P Register during the operation of Branch commands. The contents of P may be sel-ectively displayed on the console.
NOTE by jumper pins in the Memory Multiplexer (70Cl80872, sheet 22. 1).
J
Register {Counter)The J Register is a 5-bit binary counter used to con-trol the length of shifts and to accumulate the count resulting from bit count instructions. J is controlled by the micro-coded GEN 1, GEN 3 instructions or Multiply, Divide, or TIM/TOM. The contents of J may be stored into any X location (LXC) for further use. The contents of J are displayed on the console.
I Register {Instruction}
The I Register is a 24-bit register used to hold the in-struction while it is being decoded, interpreted, and executed. An additional bit ( 14) position is used in the I Register to provide for relative addressing. In addi-tion to holding the instrucaddi-tion to be executed, the I Reg-ister is also used to hold the divisor during Divide, the multiplicand during Multiply, and the TIM/TOM con-trol word during TIM/I'OM operations.
The I Register may receive data in parallel from the
4022D-T ARITHMETIC UNIT DESC-1
0 rn
"'
n...,
Ir - - - ,
Data 1 CORE MEMORY
....---'-'-'~="'---, VIA MULTIPLEXER 1
1
24
B REGISTER
1
A REGISTER
SERIAL ADDER
24
1
A A
OVERFLOW
1 0
b
T 010 0
0
L ________ - ...J
SPB
MEMORY ADDRESS GATES QUASI
3
23 18 17 15
I
A 13
REGISTER 24
10
4 0
J COUNTER
0 4
15
15
SMQ (Address Q Register)
AMW
r - - - -,
I AUTOMATIC I PROGRAM I
L
INTERRUPTJ
0 P REGISTER
15
API CONTROL
LINE FREQUENCY
TIMER
ADJUSTABLE PULSE GENERATOR
24
PARALLEL FULL ADDER
.___ _ _ _ _ 2_4 _ _ _ _ _ _ ) I/0 Channels
Pulse Source Initiator
PROGRAMMING AND MAINTENANCE
CONSOLE
Fig. DESC. 1 GE-PAC 4022D Arithmetic Unit Block Diagram
Parallel Full Adder
The Parallel Full Adder is a 24-bit full adder. Most arithmetic operations within the arithmetic and control unit are accomplished through this adder. In addition to the normal add and subtract operations. the adder has the capability of accomplishing the following logical combinations: Input/Output operations. Data transferred into the central processor unit from Input/Output devices is channeled through the adder for distribution within the arithmetic and control unit. Data transmitted from memory to specified Input/Output devices is routed through the B Register to the Adder for distri-bution outside the arithmetic and control unit. Data transmitted from the A Register is routed through the adder for distribution outside the arithmetic and con-trol unit.
Q Register (Multiplier /Quotient)
The Q Register is a pseudo register (located in core memory address 10...S..) used as an auxiliary accumu-lator (MPY and DVJJJ. The contents of Qare also used to define fields of the A and/or B Register during GEN 3 commands. The Q Register is addressed and gated to the B Register during the command execution.
Memory Address Gates
The Memory Address Gates provide selection of the core memory address bits from the desired register or control circuit.
Certain memory locations are pre-assigned for specific use. These memory locations should be used only for the purpose intended unless hardware is not included to make use of the specific reserved address. The reserved memory locations and the pre- assigned uses are listed below.
Octal
Bulk Memory Pointer Word SPB Link Storage
Quasi Operand Storage
003
40220-T ARITHMETIC UNT
Index Register
Q Register
Reserved
Unused
Memory Protect Branch Vector Memory Protect/Watchdog Instruction Storage
Reserved
Watch Dog Branch Vector
Reserved
Quasi Branch Vectors
Memory Protect Status Map
Interrupt Response Locations
Quasi Package
DESC-3
Automatic Program Interrupt Control
The Automatic Program Interrupt control logic within the Arithmetic Unit provides timing synchronization between the AU and API modules, inhibits interrupts following the execution of specific instructions., inhibits inhibitable interrupts (response addresses 300
8- 377 8) under program control and provides Echo intef'"rupts to the API when certain conditions exist.
These control functions and the associated logic ele-ments are described in the following paragraphs:
• Timing synchronization - The Enable API Gate, GlWENA (logic sheet 122) must be enabled to allow any interrupts to be ser-viced. This gate is only enabled during Time 3 Envelope (TSCA TSCB TSCC) of Sequence State 4 (AUA5) provided that an interrupt may occur following the execution of the instruction being executed.
•
When an interrupt is generated by the API module., memory is addressed from the API module ( GOSAMW) during the next Sequence State 1. This interrupt signal inhibits addressing memory from the P Register. GOSAMW enables memory ' address bit 7 (D1MA07) and in
conjunc-tion with the API Address Generator enables D1MA06-00 according to the interrupt level. In this manner an interrupt response address between 2008 and 377
8 will be selected.
A detailed description of the API module is contained in this book set.
Inhibit Interrupts following the execution of specific instructions - Interrupts must not occur following the execution of cer-tain commands to allow the operation performed by the command to be com-pleted. For instance., interrupts are not allowed immediately following GEN 1 count instructions permitting the J Regi-ster count value to be stored. Interrupts are not permitted immediately following branch instructions so that the P Register can be updated.
The following table lists those commands.
that do not permit automatic program in-terrupts following their execution and the basic logic path used to disable interrupts.
GlWENA
=
DGN1•WI08•WS67 (sh. 122)AIFlZINH (See API logic, _ _ _ 70Cl80046,, sheet 10.) considered interruptable because the ADD,, SUB.1 and LDA object instructions may be interrupted.
**
If the object instruction of XEC is interrupt-able1 XEC is considered interruptable.•
The API ENBL switch on the Programming and Maintenance console in the lockout (up) position inhibits all interrupts from occuring by disabling GlLSPl which disables GlWENA.
Inhibit inhibitable interrupts - Inhibitable or low priority interrupts (those interrupts with response addresses of 300 to 377 ) may be disabled and enabled under8
prograth control.
The· Permit Automatic Interrupt flip-flop,, Fl WPMT (logic sheet 121 ),, when reset in-hibits all inhibitable type interrupts.
Fl WPMT is reset during Time 4 Envelope
•
Clearing Fl WPMT at last pulse of State 4 inhibits inhibitable interrupts for one or more instruction following the PAI or LPR with bit 21 a "one".
Echo interrupt signals - GlWEKO (Sheet 122) applies a signal to the API to generate an
"Echo" interrupt when a TIM/TOM operation is in pr.ogress and the last character of the last word is being transferred or when a DMT command decrements the memory cell from 0 to -1. Although the Echo signal is generated whenever the DMT decrements a cell from 0 to -1, a new interrupt is gener-ated only if the DMT resulted from a previous interrupt.
A detailed description of the automatic pro-gram interrupt module is contained following the API tab in this book set.
Overflow Flip-Flop
The Overflow flip-flop, Fl UOFL (logic sheet 54), pro-vides arithmetic overflow detection during the execution of ADD, DVD, MPY, and SUB commands. In addition, the Overflow flip-flop is set during the execution of GEN 3 commands when bit 5 of the command word is a "one"
if the exclusive "OR" of A23 and A22 is a "one".
Arithmetic overflow occurs when the result of an arith-metic operation provides, or will provide, a result whose magnitude exceeds the capacity of 23 bits for of the Overflow flip-fl.op status may then be accom-pli.shed by the LPR command. command unconditionally clears the Test flip-flop.
Programming And Maintenance Console The Programming and Maintenance Console provides one method by which the operator may communicate with the computer in machine language. It allows the operator to load and execute programs and monitor the running program. A detailed description of the Console is contained under the mnemonic CON in this section.
Line Frequency Timer
The line frequency timer generates logic level nals from the 60Hz (or 50Hz) AC source. These frequency (input power frequency or twice input power frequency) of the timing signal to the API input.
The logic level pulses are wired to the Automatic Program Interrupt module providing interrupts at the pin selected rate. The associated interrupt response address contains a Decrement Memory and Test command (DMT) to accomplish a time keeping function by decrementing a count preset in a memory location. When the count passes from zero to minus one, the DMT command causes an "echo"
API signal which informs the program that a predeter-mined time period has elapsed. The program then takes whatever action is appropriate for this time in-terval and reloads the count value in the memory loca-tion decremented by the DMT command.
A schematic of the line frequency timer is contained on sheet 145 of the Arithmetic Unit logic.
4022D-T ARITHMETIC UNIT , DESC-5