below. Timing and Block Diagrams of the GEN 1 commands in Table GNl. 1 denoted by shadin~ are provided to illustrate the operation of GEN 1 com-mands. These commands were selected as being representative of all GEN 1 commands. A general description of all GEN 1 commands is presented.
Because of the similarity of commands within each group, little difficulty should be encountered in de-termining how any GEN 1 command is implemented.
Fig. GNl. 2 contains a flow chart of the functions performed during the execution of any GEN 1 com-mand.
BASIC TIMING
All GEN 1 commands are 11 fetched" during a normal Sequence Control State 1. All Gen 1 commands are executed during Sequence Control State 4. Since the execution of GEN 1 commands do not require the use of memory, Memory Request (GlSMRQ) is inhibited
during State 4. The basic timing of State 4 for all GEN 1 commands is the same. These basic timing signals are shown in Fig. GNl. 3.
The Grey Code Sequence Time Counter (Fl TSCA, B, C) is. incremented by the first six clock pulses of State 4. That is, since memory is not requested, the Sequence Time Counter cannot and does not await Data Ready and Memory Release. Because GEN 1 commands require serial shifting of the-.A Register, State 4 is extended by using the Delay Time Counter (Fl TAFF - FlTEFF) to allow sufficient time to shift the A Register and to determine when all 24 shifts have occurred.
Time 6 envelope (Fl TT6E) is entered after the first six clock pulses of State 4. Each clock pulse of Time 6 envelope increments the Delay Time Counter until it contains 308 • Allowing the Delay Time Counter to increment to 303 defines 2410 clock pulses that may be used to shift the A Register. When the Delay Ti:r;ne Counter has been incremented to 303, Last Pulse (Dl TLPE) is enabled to end the execution of the GEN 1 command.
The timing diagram also illustrates that the J Counter is always cleared (DOJJEO) and the complement of bits 4 through 0 (K bits) of the I Register are always trans-ferred to the J Counter. Operation of the J Counter and the function of the count value set in the J Counter depends on the microcoding of the GEN 1 instruction to be executed.
GNl-2 ARITHMETIC UNn 4022D-T
MNEMONIC 14 13 12 11 10 9 8 7 6 5 4 3 2 0 BIT MANIPULATION
ADO 0 0 0 1 1 1 0 0 0 O • ~ K- ....L ___.
~cB«~~W~~~~~~J<S4¥~~~
CLO O 0 0 1 0 0 0 0 1 0 1 1 1 1 1
W~oW~~~~~~~~~
~~~~~~~4Y~~-CMZ 1 1 1 0 0 0 0 1 0 0 1 1 1 1 1
0 0 0 0 0 0
0 0 0 0
CPL 0 0 0 0 0 0
IBK 0 0 0 0 0 0
LEM 0 0 0
LDO 0 0 0 0 0
LDZ 0 0 0 0 0 0 0
0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 1
1 I 1
0 0 0 0 0
.____-1_·--K-.!---r.l-~· I
0 0 0 0 0
LMO 1 1 0 0 0 0 0 0 0 0 O 0 O 0 0
RBK 0 0 0 0 0 0 0 - · - - - ' - - - - K ...
SEK 0 0 0 0 0 0 0
TEST FLIP-FLOP OPERATION
REV 0 0 0 0 0 0
RNZ 0 0 0 0 0 0 0 1 1 0 0 0
ROD 0 0 0 0 0 0 0 0 -·----K---.---,---·~
RST 0 0 0 0 0 0
SET 0 0 0 0 0 0 0
SEV 1 1 1 0 0 0 1 0 1 0 4- K . .
TES 0 0 0 0 0
TEV 0 0 0 0
TNM 1 0 0 0 0 0 0
TNZ 0 0 0 0 0 0 0 0
TOD 0 0 0 0 0 0 - 4 - - ' - - - - K - - - - -..
-TOR 0 0 0 0
TOS 0 0 0 0 ~-~---'----+--K---··
TSC 0 0 0 0 0 0 • K ....
TZC 0 0 0 0 0 0 0
TZE 0 0 0 0 0 0 0 0 0
Sf{IFT A RIGHT
W
~ Timing and Block diagrams of the GEN 1 commands denoted by shading are provided in the following text and are representative of the different types of GEN 1 commands.':' These commands are not recognized by the standard assembler.
Table GNl, 1 Microcoded Bit Configuration of GEN 1 Commands
4022D-T ARITHMETIC UNIT GN1~3
GNl-4
AR23 - A Input of Serial Adder
Reset Test F /F
Is IR06 = 1
YES
NO
AROO-+ A Input of Serial Adder
-;TATE 4
C.lear J Counte;J and Delay Time
Counter
-·---· -~
IS IR12 = 1 NO
YES IS !Rl1 = 1
I~:=., A Input -
-1
AROO - A Input
L_~r
_
_.~~rial Adder_~______ L ___ ~--
L o f Serial Adder _Jr
-YES
NO Set Test F /F
Set J = I 4_ Set Enable J Counter 0 Flip-Flop (FlJENJ)
Is IR07 = 1 NO
Enable Delay Time Counter.
Increment at each clock pulse.
YES Set Carry Control
Flip-Flop, FlAFNP
From sheet GNl- D 1 - - - 1 9 1
_ _ _ _ _ _ _i_---..., YES Disable Shifting of A Register Is Delay Time Counter = 308
NO
Enable Shift Right of A Register gate (GOASRl).
ES
NO
Fig. GNl. 2 CENl Flow Chart
ARITHMETIC UNIT
Disable incrementing of J Counter.
To Page GNl-5
Disable Shift Right of A Register Gate (GOASRl).
4022D-T
40220-T
No
Arm Test Fllp-Fllp to ~t
Ill IR09" I YES
YES
NO
NO
-~From P.tge c.;Nl-4~
,--;-;;:T·~ \_
NO - - · · NO B~~05 = _l _ __.,r----~_:_ 37 ___
::>---·
YE'l ---·-··-
_==-=rv-Es
NO
NO
YES Ill IRIO = 1
~r~-1-.T~s.t Fllp-Flop
L ___
--~R_e~s_e_t _ _ _ _ ~09 = l
NO 0--+B Input
of Serlal Adder
AROO-+ B Input
ot Serlal Adder
[J --- - -,
AROO .... B Input f Serial Adder
J
NO
NO
NO
~--- __ T _____ _
Is A In)lllt to '3erlal Adder • 1
YES Is B Input to Serlal Adder • 1
YES Arm Full Adder Carry Fllp- Flop (FlAFNP) to Set
Ill B Input to Serlal Adder = 1
YES
NO
YES
ls Shlft Rlght of A NO Register gated (GOASRI) Enabled
YES
NO Is Full Adder Carry Flip-Flop (FlAFNP) ')et
Is Full Adder Carry Fllp-Flop (FlAFNP) Set
YES
YES
NO
-~ES lll····A Input to . .. ·-'lerlal Adder = 1 --·-~
NO~i
Is B Input t
[ _ . ., .. , E.CJ
IArm Full Adder I I
Carry Flip- Flop 1
(FlAFNP) to Clear
I
-··--I-=- J
-_l__
NO / - ; ; A Input to ~ES
\__<e,lal Add"' !__j
l
Is B Input to Serial Adder = 1
ts B Input-;~·--...._), YE;~ Y~ .. ts-~ ~put to .. - ) Serlal Adder = 1 \___Serial Adder = 1
NO NO NO
Fun
Adde~-q~- outp~t:-·[J And AR23 is Armed to Set--·
-·----·---To Page GNl-6
©
Fig. GNl. 2 GEt"l Flow Chart
YES
YE
GNl-6
NO
YES
YES
Is IR06 = 1 NO Arm J Counter to be Cleared
Is J = 37 B NO
YES
Inhibit J Counter From Incrementing
(GOJINC)
From Page GN!-5 ('
ls Shift Right of A Register Gate (GOARSRl) Enabled
YES Is A Input to Serial Adder = 1
YES Is IR07 = 1 NO
Is IR06 = 1 NO YES
Arm Enable J Counter Fllp-Flop (FlJENJ) to be Cleared
Is Enable J Counter Flip-Flop (FlJENJ) Set
YES
Is IR05 = 1 NO
Is A Input To YES Serial Adder = 1
NO
ls IROB = 1 YES NO
Is IR07 = 1 NO
Is IR06 = 1 NO YES
CLOCK OCCURS: .
1. All Enabled Flip- Flops are triggered to set or clear.
2, The Delay Time Counter is incremented.
3. The J Counter is incremented, if enabled 4, The A Register is shifted 1 place right if
enabled.
To sheet GNl-4
Fig. GN 1. 2 GEN 1 Flow Ch<>.rt
ARITHMETIC UNIT
Arm J Counter To Increment (GOJINC)
4022D-T
TOT1T2Tn-fr~•
T" -CLOCK (lOMHz)I l I I I I l I I I I I I I I I l I I I l I I I I I I I I I I I I I
DlTLPE (11)
Jl~---!L_
FlSCOl (17)
I I
FlSC04 (17. 1)
_J L
FlTSCA(8)
---i__j L
FlTSCB(8)
______s--1.__~~~~~~~~~~~~~~
Fl TSCC (8) Fl TT6E (8) Fl TEFF (14)
Fl TDFF (14) Fl TCFF (14) Fl TBFF (13)
Fl TAFF (13) DOJJEO (70) (Clear J)
DlJTIJ(70)
rl~~--~~-~~~~~~~~~
CI4-o-J>
n
DOPINl,2 (88) ______J '"---~~
1"""4.---
STATE 4TLPE = TLP2 = DGNl · TT6E ·TAFF· TBFF SCOl = SSSl • TLPE • SCLK
SSS4 = SS41 · SMDQ • DBIS · MSSI SC04 SSS4 · TLPE · SCLK TCSA = TLPE · TCK2
TCSA = TMEM · TSCB • TCK2 TCSB TSCC • TCK2
TCSB = TSCC · TSCA • TCK2
TSCC (TSCA · TSCB + TLPE) · TCK2 TSCC = TSCB • TSC2 · TCK2
TT6E =
I:S.C..L = TEFF =
TEID = TEFF =
~~
TDFF
=
TMEM · TSC 1 • TCK2 TSCB · DG13 · SC04 • TSCA TEID ·JCKl
~·D2TK
T6E3 · TEID· JCKl TT6E ·(TAFF + TBF'F)
TEF'F · TEID • JCKl ·TDFF' + TTOE TEFF · TEID · JCKl · TDFF
TCFF = Gl TEFF · Gl TDFF · JCKl•TCFF + TTOE TCFF= GlTEFF·GlTDFF·JCKl•TCFF TBFF = Gl TDEF · Gl TCFF · JCKl•TBFF + TTOE TBFF = Gl TDEF · Gl TCFF · JCKl ·TBFF
TAFF= GlTDEF·GlTBCF·JCKl·TAFF +TTOE TAFF= Gl TDEF · Gl TBCF · JCKl· TAFF
JJEO JCKl · TSCA · TSCB • JS4G JS4G =DMD!• SC04
JTIJ JS4G • TSCA · TSCB · XMDV PINI, 2= PIN4
PIN4 = PIN!· BG12 ·TSCA .TSCB
Fig. GNl. 3 GEN 1 Basic Timing Diagram