BASIC TIMING OF FULL OPERAND COMMANDS

these command de-scriptions for details.

Fig. CMD. 2 contains a timing diagram and logic equa-tions of the Sequence Time Counter. This timing di-agram applies to all commands except the execution states of GEN 1, GEN 2, GEN 3, MPY, DVD, and TIM/

TOM operations. It is drawn to illustrate the sequencing when operating with a 1. 6 microsecond memory. generated from the Memory Release signal (MXDlMRLS), applied by the Core Memory module at the end of the

Re-CMD-2 ARITHMETIC UNIT 4022D-T

lOMHz CLOC Dl TLPE(ll) (Last Pulse) F1TSCA(8)

Fl TSCB(8) Fl TSCC(S) Gl TSC2( 9)

100 NS-+I

l.-:;::27

NS•l

14-G1SMRQ(22) (Memory Request)

M X D 1 M D R 4 ( 1 0 ) * -(Data Ready)

MXDlMRLS( 10)* _ _ ____.

(Memory Release)

MXF 1MTC1( 9 )>.'<

MXF1MTC2(9)* ' -MXF 1MTC3(9 )>:c

MXF1MTC4(9)*

n

I

^TO

^I

^Tl

^{I ---}

^T2

^I

^T3

^I

^T4

^I+-

^TS

--+I

- - - A U C Y C L E

-1

• 4 M E M O R Y C Y C L E -(1. 6 µsec)

':'Memory Control logic - '70Cl80872

Q)

^TLPE⁼^TLPl

⁼

MRLS • CMAN • TLPE

@

^TSCA

=

MDR4 • CTAE • TCK2 TSCA

=

TLPE • TCK2

G)

^TSCB

=

TSCA • TSCC • TCK2 TSCB

=

TSCC • TCK2

<})

TSCC

=

TSC2 • TSCB • TCK2

TSCC

=

TSCA • TSCB • TCK2 + TLPE • TCK2

@

TSC2

=

TSCA

@

SMRQ

=

MRLS • (DG12 + BC12) • LMRQ • SRQ2 • CMAN + SRQl • TSCA • CMAN • LMRQ

Fig. CMD. 2 Basic Timing Diagram. Full Operand Commands

+3. 5V

ov

©

®

©

®

@

quest is normally enabled by the Memory Release (MXDlMRLS) signal generated in the memory. If, how-ever, the previous or next cycle does not require mem-ory access (i.e., State 4 of GEN 1 or GEN 2 command, or when State 4 is extended for the execution of GEN 3, MPY, DVD, or TIM/TOM), the Memory Request signal is inhibited until Time 0 Envelope. Fig. CMD. 3 illus-trates the timing relationships for both types of memory requests.

Instruction Sequencing

All instructions performed by the 4022C Arithmetic Unit follow a definite set pattern or sequence for "fetching"

the instruction from memory, performing index address modification if required, and executing the instruction.

Sequence Control State flip-flops FlSCOl, FlSC02, F1SC03, Fl SC04, and FlSC05 are provided to control this pattern or sequence.

Fig. CMD. 4 graphically illustrates the Sequence States required to fetch, index, and execute any instruction.

Briefly, the function performed during each Sequence Control State is described below.

•

Sequence Control State 1 - FlSCOl: During this Sequence State, all commands are

"fetched" from memory. Non-indexed XEC, BRU, BTR, and BTS commands are also executed during Sequence Control State 1.

FlSCOl TIM/TOM

YES

YES (XEC + BRU + BTR +

YES

F1SC02

BTS)·X 0 NO

DMT + (X

=

d · LXK)

(XEC + TXH + BRU + BTR + BTS)

YES

•

Sequence Control State 2 - F 1 SC02: During Sequence State 2 index address modification occurs. Also, STX, TXH, and DMT com-mands use State 2 for a portion of the exe-cution.

Sequence Control State 3 - FlSC03: State 3 is used during the execution of MPY, DVD, STQ, STX, and TIM/TOM operations.

Sequence Control State 4 - F 1SC04: State 4 is the execution state for most commands.

Sequence Control State 5 - FlSC05: State 5 is used during MPY, DVD, GEN 3, STQ, LDQ, and TIM/TOM instructions to complete their execution cycle.

Sequence Control State l

Sequence Control State 1 defines the ¹¹fetch" cycle for all instructions. Because St~te 1 is nearly the same for all commands, it is not described in the command de-scriptions later in this section unless it performs unique functions (e.g., XEC, BRU, TXH, BTR, and BTS).

Therefore, the following discussion describes the de-tailed operation of the Arithmetic Unit during State 1.

This discussion applies to all commands.

F1SC03

YES

NO. NO

YES

F1SC05 MPY + DVD + GN3 + STQ + - - - i

LDQ + TIM + TOM F1SC04

Fig. CMD. 4 Instruction Sequencing

CMD-4 ARITHMETIC UNIT 4022D-T

lOMHz Clock AU Timing Envelopes GlSMRQ(22) (Memory Request) MXF1MPR4(7)*

f/ lO Jl. .U J.'5 if 15 i J. ~ f ⁵ ^" ⁷ ⁸ ^~J.0 1:L J. Z ,15 .t4 .J.5' 1'

MXF1MDR4(10)':--_

---J

(Data Ready)

MXFlMRLS(lO)':< _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...

n.._ _______________ ^n

(Memory Release) MXF1MTC1(9)* _ _ o_...j

MXF1MTC2(9)* _ _ _ ___, MXF1MTC3(9)* _ _ _ _ _ ___,

MXF1MTC4(9)>:' _ _ _ _ _ _ _ _ _ _ __,

.,__ _ _ _ _ _ AU C Y C L E - - - • ...

~t---1-AA.1.U

C Y C L E - - - • ....

141MEMORY CYCLE14MEMORY C Y C L E -Memory Operation Initiated

Following the Rest State

(i.e.~ no requests present)

Memory Operation Initiated By a Successive AU Request ':'Memory Control Logic - 70Cl80872

Fig. CMD. 3 AU/Memory Cycle Relationship

L

Fig. CMD. 5 contains a block diagram of the Arithmetic Unit operation during a normal Sequence State 1. A timing diagram and logic equations for State 1 are con-tained in Fig. CMD. 6. Refer to these aids during the following discussion.

During Sequence State 1, memory is always requested (GlSMRQ) to ''fetch" the next command fro:rn memory.

Memory is addressed from the P Register during State 1 except when following a branch instruction (SPB., BRU, BTS, BTR, LDP, or LPR), an XEC command, an Auto-matic Program Interrupt, a Memory Protect Error, or when a new Protect Status Word is required for the op-tional Memory Protect logic. Upon receipt of the Data Ready signal from the core memory module, the com-mand located in the addressed memory location is gated to the B Register by DlBMEM. Bits 23 through 14 of

the command are gated from B to the I Register (IBXI).

This places the OP Code of the instruction fetched in the I Register where it is decoded and the operation to be performed is determined. The operand address portion of tile command (bits 13 -0) is gated to the I Register via the Adder Unit. If the command is relative ad-dressed (bit 14 is a "one"), relative address modifica-t.ian of the operand address occurs in the Adder Unit prior to being transferred to the I Register. Relative Addressing is described later in this section.

At memory release, Last Pulse Envelope is enabled to end Sta.te 1. Sequencing will then continue for exec u -tion of the command as described under the

mnemon-ic of the command.

r---.,

B23-0 UBAU

Fig. CMD. 5

CMD-6

I CORE I I :\IE :\IOR y I

I :\IODl' LE I

L.---.J

ADDER

MEMORY ADDRESS GATES

SAMP

114

State 1 Block Diagram

4022D-T

TOE - - i ~ TlE

I'

^{I t}1 -1 2 3 4 5

T3E

r-

^T4E

t 1--

TSE - I

13 14 15 16

10 MHz Clock

_fl

^+3.5V

_ov

DlTLPE (11) (Last Pulse)

Fl TSCA (8) Fl TSCB (8) FlTSCC (8) FlSCOl (17) (State 1) GlSMRQ (22) (Memory Request)

DlSAMP _ _ _ _ __.

(Address Memory From P)

DlBCLR (39) (Clear B) D1MDR4 (10) (Data Ready) MXDlMRLS (10) (Memory Release) DlBMEM (39)

- - - '

---0

.____Q)

0 0

.____G)

0 .___G)

(Memory Data B)

________________________

^___.

DllBXI (81) (B23-14-.I) DlUBAU (50)

(B23-0~AU)

DlWLI (80) DlIUIL (PAU14-0-+l)

CD

TLPE = TLPl = MRSL. CMAN. TLPE

®

TSCA = MDR4 • CTAE • TCK2 TSCA = TLPE • TCK2

®

TSCB = TSCA • TSCC • TCK2 TSCB = TSCC • TCK2

@

TSCC = TSC2 • TSCB • TCK2

TSCC = TSCA · TSCB • TCK2 + TLPE • TCK2

®

SCOl = SSSl • TLPE • SCLK

SCOl = TLPE • (SR12 + SR14) • TSLK

..._ @ '----@

@

SMRQ = MRLS · DG12 • SRQ2 • CMAN • LMRQ + SRQl • TSCA • CMAN • LMRQ

G)

SAMP = MAMV · MTRP • SCOl • XRMF • SEXC • SPil

®

BCLR = BCLl = STOR · TSCA ·TSCC·BCLK· BMRQ

®

BMEM= MDR4 • STOR • BMRQ • BCLK

@

IBXI = ISAV · TSCB • HTTF • MSSI • SCOl • !SCA• TSCC

(!}

UBAU = UBA3 = SCOl • TSCA · UBBl • UAMV

@

IULI, U = IULl

Fig. CMD. 6 Sequence Control State 1 Timing Diagram

ARITHMETIC UNIT CMD-7

c

0 tlD

s .s

s

~ ...

Q) E--t

u 0

INDEXING

Indexing of a command involves the changing of the command operand by adding it to the contents of a designated X core cell (core cells 1 through 7). The GE-PAC command format allocates 3 bits (15, 16, and 17) to specify Index Address Modification.

When bits 15, 16, and 17 are not equal to zero1 the 14

10 memory locations.

To illustrate the effect of indexing address modifica-tion, refer to CMD. 7 and consider the following

Following execution of the command (LDA) ·in location 1000 instruction control rather than for index address modi-fication. These commands are:

INX change the intelligence of the microcoding. Therefore, caution must be exercised when specifying index ad-dress modification of these commands.

Indexing of any command requires the use of Sequence ,(DlIULI,, IL), to complete the indexing address

mba1-fication operation. The next Sequence State would then be entered and memory addressed from the I

CMD-8 ARITHMETIC UNIT 4022D-T

BMEM

IS INDEXING SPECIFIED YES

ARITHMETIC UNIT CMD-9

Im Dokument co·MPUTER PROCESS (Seite 117-125)