4. Store Floating-Point Single
4.4 Floating-Point Exceptions
This architecture defines the following floating-point exceptions:
• Invalid Operation Exception SNaN
Infinity-Infinity Infinity+ Infinity Zero+ Zero
InfinityxZero Invalid Compare Software Request Invalid Square Root Invalid Integer Convert
• Zero Divide Exception
• Overflow Exception
• Underflow Exception
• Inexact Exception
These exceptions may occur during execution of computational instructions. In addition, an Invalid Operation Exception occurs when a Floating-Point Status and Control Register instruction sets FPSCRvx-SOFT to 1 (Software Request). An Invalid Square Root exception can occur only if at least one of the Floating Square Root instructions defined in Appendix A, "Optional Instructions," on page 197, is implemented.
Each floating-point exception, and each category of Invalid Operation Exception, has an exception bit in the FPSCR. In addition, each floating-point exception has a corresponding enable bit in the FPSCR. The excep-tion bit indicates occurrence of the corresponding excepexcep-tion. If an excep-tion occurs, the corresponding enable bit governs the result produced by the instruction and, in conjunction with the FEO and FEl bits (see page 153), whether and how the system floating-point enabled exception error handler is invoked. (In general, the enabling specified by the enable bit is one of invoking the system error handler, not of permitting the exception to occur. The occurrence of an exception depends only on the instruction and its inputs, not on the setting of any control bits. The only deviation from this general rule is that the occurrence of an Underflow Exception may depend on the setting of the enable bit.)
The Floating-Point Exception Summary bit (FX) in the FPSCR is set to 1 by any floating-point instruction, except mtfsfi and mtfsf, that causes any of the floating-point exception bits in the FPSCR to change from 0 to 1, or by a mtfsfi, mtfsf, or mtfsb1 instruction that explicitly sets the bit to 1. The Floating-Point Enabled Exception Summary bit (FEX) in the FPSCR is set when any of the exceptions is set and the exception is enabled (enable bit is 1).
A single instruction, other than mtfsfi or mtfsf, may set more than one exception only in the following cases:
• Inexact Exception may be set with Overflow Exception.
• Inexact Exception may be set with Underflow F"""!'tion_
• Invalid Operation Exception (SNaN) is set with Invalid Operation Exception(= x 0) for Multiply-Add instructions for which the values being multiplied are infinity and zero and the value being added is an SNaN.
• Invalid Operation Exception (SNaN) may be set with Invalid Opera-tion ExcepOpera-tion (Invalid Compare) for Compare Ordered instructions.
• Invalid Operation Exception (SNaN) may be set with Invalid Opera-tion ExcepOpera-tion (Invalid Integer Convert) for Convert to Integer instructions.
When an exception occurs the instruction execution may be sup-pressed or a result may be delivered, depending on the exception.
Instruction execution is suppressed for the following kinds of excep-tion, so that there is no possibility that one of the operands is lost.
• Enabled Invalid Operation
• Enabled Zero Divide
For the remaining kinds of exception, a result is generated and written to the destination specified by the instruction causing the exception. The result may be a different value for the enabled and disabled conditions for some of these exceptions. The kinds of exception that deliver a result are the following.
• Disabled Invalid Operation
• Disabled Zero Divide
• Disabled Overflow
• Disabled Underflow
• Disabled Inexact
• Enabled Overflow
• Enabled Underflow
• Enabled Inexact
Subsequent sections define each of the floating-point exceptions and specify the action that is taken when they are detected.
The IEEE standard specifies the handling of exceptional conditions in terms of "traps" and "trap handlers." In this architecture, an FPSCR exception enable bit of 1 causes generation of the result value specified in the IEEE standard for the "trap enabled" case: the expectation is that the exception will be detected by software, which will revise the result. An FPSCR exception enable bit of 0 causes generation of the "default result"
value specified for the "trap disabled" (or "no trap occurs" or "trap is not implemented") case: the expectation is that the exception will not be detected by software, which will simply use the default result. The result to be delivered in each case for each exception is described in the sections below.
The IEEE default behavior when an exception occurs is to generate a default value and not to notify software. In this architecture, if the IEEE default behavior when an exception occurs is desired for all exceptions, all FPSCR exception enable bits should be set to 0 and Ignore Exceptions Mode (see below) should be used. In this case the system floating-point enabled exception error handler is not invoked, even if floating-point exceptions occur: software can inspect the FPSCR exception bits if neces-sary, to determine whether exceptions have occurred.
In this architecture, if software is to be notified that a given kind of exception has occurred, the corresponding FPSCR exception enable bit must be set to 1 and a mode other than Ignore Exceptions Mode must be used. In this case the system floating-point enabled exception error han-dler is invoked if an enabled floating-point exception occurs.
The FEO and FE1 bits control whether and how the system point enabled exception error handler is invoked if an enabled floating-point exception occurs. The location of these bits and the requirements for altering them are described in Book III, Section 2.2.3, "Machine State Register," on page 374 and Chapter 7, "Synchronization Requirements for Special Registers and for Lookaside Buffers," on page 483. (The sys-tem floating-point enabled exception error handler is never invoked because of a disabled floating-point exception.) The effects of the four possible settings of these bits are as follows.
FEO FE1 Description 0 0
0 1
Ignore Exceptions Mode
Floating-point exceptions do not cause the system floating-point enabled exception error handler to be invoked.
Imprecise Nonrecoverable Mode
The system floating-point enabled exception error handler is
Programming Note In any of the three non-Precise modes. a Fln:.ting-Point Status and Control Register instruction can be used to force any exceptions, due to instructions initiated before the Floating-Point Status and Control Register instruction, to be recorded in the FPSCR.
(This forcing is superfluous for Precise Mode.)
In either of the Imprecise modes, a Floating-Point Status and Control Register instruction can be used to force any invocations of the system floating-point enabled instruction, to occur. (This forcing has no effect in Ignore Exceptions Mode and is superfluous for Precise Mode.)
A sync instruction, or any other execution synchronizing instruction or event (e.g., isync: see Book II, "Instruction Synchronize XL-form,"
on page 346), also has the effects described above. However, in order to obtain the best performance across the used to obtain these effects.
1 0
1 1
the enabled exception. It may not be possible to identify the ex-cepting instruction or the data that caused the exception. Re-5uh:5 p;:0Jm .. nl
uy
the excepting instruction may have been used by or may have affected subsequent instructions that are exe-cuted before the error handler is invoked.Imprecise Recoverable Mode
The system floating-point enabled exception error handler is invoked at some point at or beyond the instruction that caused the enabled exception. Sufficient information is provided to the error handler that it can identify the excepting instruction and the operands, and correct the result. No results produced by the excepting instruction have been used by or have affected subsequent instructions that are executed before the error han-dler is invoked.
Precise Mode
The system floating-point enabled exception error handler is invoked precisely at the instruction that caused the enabled ex-ception.
In all cases, the question of whether a floating-point result is stored, and what value is stored, is governed by the FPSCR exception enable bits, as described in subsequent sections, and is not affected by the value of the FEO and FEl bits.
In all cases in which the system floating-point enabled exception error handler is invoked, all instructions before the instruction at which the system floating-point enabled exception error handler is invoked have completed, and no instruction after the instruction at which the system floating-point enabled exception error handler is invoked has been exe-cuted. (Recall that, for the two Imprecise modes, the instruction at which the system floating-point enabled exception error handler is invoked need not be the instruction that caused the exception.) The instruction at which the system floating-point enabled exception error handler is invoked has not been executed unless it is the excepting instruction, in which case it has been executed if the exception is not among those listed on page 152 as suppressed.
In order to obtain the best performance across the widest range of implementations, the programmer should obey the following guidelines.
• If the IEEE default results are acceptable to the application, Ignore Exceptions Mode should be used with all FPSCR exception enable bits set to 0.
• If the IEEE default results are not acceptable to the application, Impre-cise Nonrecoverable Mode should be used, or ImpreImpre-cise Recoverable Mode if recoverability is needed, with FPSCR exception enable bits set to 1 for those exceptions for which the system floating-point enabled exception error handler is to be invoked.
• Ignore Exceptions Mode should not, in general, be used when any FPSCR exception enable bits are set to 1.
• Precise Mode may degrade performance in some implementations, perhaps substantially, and therefore should be used only for debugging and other specialized applications.
4.4.1 Invalid Operation Exception
Definition
An Invalid Operation Exception occurs whenever an operand is invalid for the specified operation. The invalid operations are:
• Any floating-point operation on a signaling NaN (SNaN).
• For add or subtract operations, magnitude subtraction of infinities (00-00)
• Division of infinity by infinity (oo + oo)
• Division of zero by zero (0 + 0)
• Multiplication of infinity by zero (oo x 0)
• Ordered comparison involving a NaN (Invalid Compare)
• Square root or reciprocal square root of a negative (and nonzero) number (Invalid Square Root)
• Integer convert involving a large number, an infinity, or a NaN (Invalid Integer Convert)
In addition, an Invalid Operation Exception occurs if software explic-itly requests this by executing an mtfsfi, mtfsf, or mtfsb1 instruction that sets FPSCRvxsoFT to 1 (Software Request). An Invalid Square Root exception can occur only if at least one of the Floating Square Root instructions defined in Appendix A, "Optional Instructions," on page 197, is implemented.
Programming Note The purpose of FPSCRvxsoFT is to allow software to cause an Invalid Operation Exception for a condition that is not necessarily associated with the execution of a floating-point instruction. For example, it might be set by a program that computes a square root, if the source operand is
Action
Exception Enable bit of the FPSCR.
When Invalid Operation Exception is enabled (FPSCRvFl) and Invalid Operation occurs or software explicitly requests the exception, then the following actions are taken:
1. One or two Invalid Operation Exceptions are set
FPSCRvxsNAN (if SNaN)
FPSCRvxrsr (if 00 - 00 ) FPSCRvxmr (if 00 + 0 0 )
FPSCRvxznz (if 0 + 0) FPSCRvxrMZ (if 00 x 0)
FPSCRvxvc (if invalid compare)
FPSCRvxsoFT (if software request) FPSCRvxsQRT (if invalid square root) FPSCRvxcvr (if invalid integer convert)
2. If the operation is an arithmetic, Floating Round to Single-Precision, or convert to integer operation,
the target FPR is unchanged FPSCRpR FI are set to zero FPSCRFPRF is unchanged 3. If the operation is a compare,
FPSCRFR FI c are unchanged
FPSCR FPCC is set to reflect unordered 4. If software explicitly requests the exception,
FPSCRpR FI FPRF are as set by the mtfsfi, mtfsf, or mtfsb1 instruc-tion
When Invalid Operation Exception is disabled (FPSCRvE=O) and Invalid Operation occurs or software explicitly requests the exception, then the following actions are taken: