Fixed-Point Store Instructions

The contents of register RS are stored into the byte, halfword, word, or doubleword in storage addressed by EA.

Byte order of PowerPC is Big-Endian by default; see Appendix D, "Lit-tle-Endian Byte Ordering," on page 233 for PowerPC systems operated with Little-Endian byte ordering.

Many of the Store instructions have an "update" form, in which regis-ter RA is updated with the effective address. For these forms, the follow-ing rules apply.

• If RAt:O, the effective address is placed into register RA.

• If RS=RA, the contents of register RS are copied to the target storage element, and then EA is placed into RA (RS).

Store Byte D-form

stb RS,D(RA)

38 I 11 RA D

i f RA = 0 then b f- 0 el s e b f- ( RA ) EA f- b + EXTS(D)

MEM(EA, 1) f- CRSls6:63

Let the effective address (EA) be the sum (RAIO)+D. (RS)s6:63 are stored into the byte in storage addressed by EA.

Special Registers Altered None

Store Byte Indexed X-form

st bx RS,RA,RB

31 I 11 RA

if RA= 0 then bf- 0

e 1 s e b f- ( RA l EA f- b + (RB)

MEMCEA, 1) f- CRS)s6:63

I

¹⁶ RB 215

Let the effective address (EA) be the sum (RAIO)+(RB). (RS)s6:63 are stored into the byte in storage addressed by EA.

Special Registers Altered None

Store Byte with Update D-form

st bu RS,D(RA)

39 RS I 11 RA

EA~ (RA) + EXTS(D) MEMCEA, 1) ~ (RS)s6:63 RA ~ EA

D

Let the effective address (EA) be the sum (RA)+D. (RS)s6:63 are stored into the byte in storage addressed by EA.

EA is placed into register RA.

If RA=O, the instruction form is invalid.

Special Registers Altered None

Store Byte with Update Indexed X-form

stbux RS,RA,RB

31 I 11 RA

EA~ (RA)+ (RB) MEM(EA, 1) f--- (RS)56:63 RA ~ EA

I 16 RB 247

Let the effective address (EA) be the sum (RA)+(RB). (RS)s6:63 are stored into the byte in storage addressed by EA.

EA is placed into register RA.

If RA=O, the instruction form is invalid.

Special Registers Altered None

Store Halfword D-form

sth RS,D(RA)

44 I 11 RA ^D

if RA ~ O then b <-- O el s e b <-- ( RA) EA <-- b + EXTS(D)

MEM(EA, 2) <-- (RS)48:63

Let the effective address (EA) be the sum (RAIO)+D. (RS)48:63 are stored into the halfword in storage addressed by EA.

Special Registers Altered None

Store Halfword Indexed X-form

sthx RS,RA,RB

31 I ¹¹ RA

I

¹⁶ RB

if RA~ 0 then b <-- 0 e l s e b <-- ( RA ) EA <-- b + (RB)

MEM(EA, 2) <-- (RSl4s:63

407

Let the effective address (EA) be the sum (RAIO)+(RB). (RS)48:63 are stored into the halfword in storage addressed by EA.

Special Registers Altered None

Store Halfword with Update D-form

sthu RS,D(RA)

45 I 11 RA

EA<-- (RA)+ EXTS(D) MEM(EA, 2) <-- (RS)4s:63

D

Let the effective address (EA) be the sum (RA)+D. (RS)48:63 are stored into the halfword in storage addressed by EA.

EA is placed into register RA.

If RA=O, the instruction form is invalid.

Special Registers Altered None

Store Halfword with Update Indexed X-form

sthux RS,RA,RB

31 l11 RA

EA+--- (RA) + (RB) MEM( EA. 2) +--- (RS )48:63 RA +--- EA

I

¹⁶ RB 439

Let the effective address (EA) be the sum (RA)+(RB). (RS)48:63 are stored into the halfword in storage addressed by EA.

EA is placed into register RA.

If RA=O, the instruction form is invalid.

Special Registers Altered None

Store Word D-form

stw RS,D(RA)

[Power mnemonic: st]

I 36

lo

^{I 6 RS}

I RA I I ¹¹ I 16

if RA= 0 then b +--- 0 el s e b +--- ( RA ) EA +--- b + EXTS(D)

MEM(EA, 4) +--- (RS)32:63

D

Let the effective address (EA) be the sum (RAIO)+D. (RS)32:63 are stored into the word in storage addressed by EA.

Special Registers Altered None

Store Word Indexed X-form

stwx RS,RA,RB

[Power mnemonic: stx]

31 RS I 11 RA I 16 RB 151

if RA = 0 then b ^{f -} 0 e 1 s e b ^{f - (} RA)

EA f - b + CRB)

MEM(EA, 4) f - CRSl32:63

Let the effective address (EA) be the sum (RAIO)+(RB). (RSl32:63 are stored into the word in storage addressed by EA.

Special Registers Altered None

Store Word with Update D-form

stwu RS,D(RA)

[Power mnemonic: stu]

37 RS

I 11 RA EA f - (RA) + EXTSCD)

MEM(EA, 4) f - CRSl32:63 RA f - EA

D

Let the effective address (EA) be the sum (RA)+D. (RS)32:63 are stored into the word in storage addressed by EA.

EA is placed into register RA.

If RA=O, the instruction form is invalid.

Special Registers Altered None

Store Word with Update Indexed X-form

stwux RS,RA,RB

[Power mnemonic: stux]

31 _I

11 RA EA f- (RA) + (RB)

MEMCEA, 4) f- CRS)3z:63 RA f- EA

I 16 RB 183

Let the effective address (EA) be the sum (RA)+(RB). (RSlJ2:63 are stored into the word in storage addressed by EA.

EA is placed into register RA.

If RA=O, the instruction form is invalid.

Special Registers Altered None

Store Doubleword OS-form

std RS,DS(RA)

62 I 11 RA

if RA= 0 then bf- 0 e l s e b f- C RA ) EA f- b + EXTS(OSllObOO) MEMCEA, 8) f- CRS)

DS

Let the effective address (EA) be the sum (RAIO)+(DSiiObOO). (RS) is stored into the doubleword in storage addressed by EA.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered None

Store Doubleword Indexed X-form

stdx RS,RA,RB

lo

^{31 16 RS}

I

^{11 RA}

I

^{16 RB}

_I

₂₁ ¹⁴⁹

_~(I

if RA = 0 then b f- 0

else b f- (RA)

EA f- b + (RB) MEM(EA, 8) f- (RS)

Let the effective address (EA) be the sum (RAIO)+(RB). (RS) is stored into the doubleword in storage addressed by EA.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered None

Store Doubleword with Update OS-form

stdu RS,DS(RA)

62 RS

I

¹¹ RA

EA f- (RA) + EXTSCDSllObOO) MEM(EA, 8) f- (RS)

RA f- EA

DS

Let the effective address (EA) be the sum (RA)+(DSiiObOO). (RS) is stored into the doubleword in storage addressed by EA.

EA is placed into register RA.

If RA=O, the instruction form is invalid.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered None

Programming Note In some

implementations, the load Byte-Reverse instructions may have greater latency than other load instructions.

Store Doubleword with Update Indexed X-form

stdux RS,RA,RB

31 RS

EA +-- ( RA) + (RB) MEMCEA, 8) +-- (RS) RA +-- EA

I 16

^{RB 181}

Let the effective address (EA) be the sum (RA)+(RB). (RS) is stored into the doubleword in storage addressed by EA.

EA is placed into register RA.

If RA=O, the instruction form is invalid.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered None

3.3.4 Fixed-Point Load and Store with Byte

Im Dokument BUSl, ~ESS (Seite 96-103)