Fixed-Point Arithmetic Instructions

The XO-form Arithmetic instructions with Rc=l, and the D-form Arith-metic instruction addic., set the first three bits of CR Field 0 as described in Section 3.3.8, "Other Fixed-Point Instructions," on page 80.

addic, addic., sub-fie, addc, subfc, adde, subfe, addme, subfme, addze, and subfze always set CA, to reflect the carry out of bit 0 in 64-bit mode and out of bit 32 in 32-bit mode. The XO-form Arithmetic instructions set SO and OV when OE=l to reflect overflow of the result. Except for the Multiply Low and Divide instructions, the setting of these bits is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For XO-form Multiply Low and Divide instructions, the setting of these bits is mode-independent, and reflects overflow of the 64-bit result for mulld, divd, and divdu, and overflow of the low-order 32-bit result for mullw, divw, and divwu.

Extended mnemonics for addition and subtraction

Several extended mnemonics are provided that use the Add Immediate and Add Immediate Shifted instructions to load an immediate value or an address into a target register. Some of these are shown as examples with the two instructions.

The PowerPC Architecture supplies Subtract From instructions, which subtract the second operand from the third. A set of extended mnemonics is provided that use the more "normal" order, in which the third operand is subtracted from the second, with the third operand being either an immediate field or a register. Some of these are shown as examples with the appropriate Add and Subtract From instructions.

See Appendix C, "Assembler Extended Mnemonics," on page 215 for additional extended mnemonics.

Programming Note Instructions with the OE bit set or which set CA may execute slowly or may prevent the execution of subsequent instructions until the operation is completed.

Programming Note Notice that CR Field 0 may not reflect the

"true" (infinitely precise) result if overflow occurs.

Programming Note addi, addis, add, and subf are the preferred instructions for addition and subtraction, because they set few status bits.

Notice that addi and addis use the value 0, not the contents of GPR 0, if RA=O.

Add Immediate D-form

addi RT,RA,SI

[Power mnemonic: cal]

14

if RA= 0 then RT f- EXTSCSI)

else RT f- (RA) + EXTS(SI) The sum (RAIO)+ SI is placed into register RT.

Special Registers Altered None

Extended Mnemonics:

SI

Examples of extended mnemonics for Add Immediate:

Extended:

Ii Rx, value la Rx,disp(Ry) subi Rx,Ry,value

Equivalent to:

addi Rx,0,value addi Rx,Ry,disp addi Rx,Ry,-value Add Immediate Shifted D-form

ad dis RT,RA,SI

[Power mnemonic: cau]

lo

¹⁵

16

^RT

111

^RA

116

^SI

i f RA. 0 then RT ~ CVTC' _{L / \ I ..JI.} f C' _J.L T II 160) II

else RT f- C RA) + EXTSCSI _II ¹⁶⁰⁾

The sum (RAIO) + (SI

II

OxOOOO) is placed into register RT.

Special Registers Altered None

Extended Mnemonics:

Examples of extended mnemonics for Add Immediate Shifted:

Extended:

[Power mnemonics: cax, cax., caxo, caxo.]

31 I

11

RA I

16

RB

Subtract From XO-form

subf RT,RA,RB

Extended Mnemonics:

Example of extended mnemonics for Subtract From:

Extended:

sub Rx,Ry,Rz

Equivalent to:

subf Rx,Rz,Ry Add Immediate Carrying D-form

addic RT,RA,SI

[Power mnemonic: ai]

12

111

RA

RT f- (RA) + EXTS(SI)

The sum (RA) + SI is placed into register RT.

Special Registers Altered CA

Extended Mnemonics:

SI

Example of extended mnemonics for Add Immediate Carrying:

Extended: Equivalent to:

subic Rx,Ry,value addic Rx,Ry,-value Add Immediate Carrying and Record D-form

addic. RT,RA,SI

[Power mnemonic: ai.]

I I

a

I

~T

16 ^{> U I} _I '""' ^DA

~1

13

RT f- CRA ) + EXT S ( S I )

The sum (RA) +SI is placed into register RT.

Special Registers Altered CRO CA

Si

Programming Note The setting of CA by the Add and Subtract From instructions, including the Extended versions thereof, is mode-dependent. If a sequence of these instructions is used to perform extended-precision addition or subtraction, the same mode should be used throughout the sequence.

Extended Mnemonics:

Example of extended mnemonics for Add Immediate Carrying and Record:

Extended: Equivalent to:

subic. Rx,Ry,value addic. Rx,Ry,-value Subtract From Immediate Carrying D-form

subfic RT,RA,SI

[Power mnemonic: sfi]

8

RT~ -,(RA)+ EXTS(SI) + 1

The sum -,(RA) +SI+ 1 is placed into register RT.

Special Registers Altered CA

Add Carrying XO-form addc

addc.

addco addco.

RT,RA,RB RT,RA,RB RT,RA,RB RT,RA,RB [Power mnemonics: a, a., ao, ao.]

31

I

¹¹ RA

RT~ CRA) + (RB)

I

¹⁶ RB

The sum (RA)+ (RB) is placed into register RT.

Special Registers Altered CA

CRO

so ov

SI

(OE=O Rc=O) (OE=O Rc=l) (OE=l Rc=O) (OE=l Rc=l)

10

(if Rc=l) (if OE=l)

Subtract From Carrying XO-form

[Power mnemonics: sf, sf., sfo, sfo.]

31

I

¹¹ RA

Example of extended mnemonics for Subtract From Carrying:

Extended:

subc Rx,Ry,Rz

Add Extended XO-form adde

[Power mnemonics: ae, ae., aeo, aeo.j 31

1

₁₁ RA I 16 RB

RT~ (RA) + (RB) +CA

The sum (RA)+ (RB)+ CA is placed into register RT.

Special Registers Altered

Subtract From Extended XO-form

Add to Minus One Extended XO-form addme

[Power mnemonics: ame, ame., ameo, ameo.]

31 _I

Subtract From Minus One Extended XO-form

[Power mnemonics: sfme, sfme., sfmeo, sfmeo.]

31

116 ///

Add to Zero Extended XO-form addze

[Power mnemonics: aze, aze., azeo, azeo.]

31 _I

Subtract From Zero Extended XO-form

[Power mnemonics: sfze, sfze., sfzeo, sfzeo.]

31 I

11

RA

116

Ill

If executing in 64-bit mode and register RA contain the most negative 64-bit number (Ox8000_0000_0000_0000), the result is the most nega-tive number and, if OE=l, OV is set to 1. Similarly, if executing in 32-bit mode and (RA)32:63 contains the most negative 32-bit number (Ox8000_0000), the low-order 32 bits of the result contain the most neg-ative 32-bit number and, if OE=l, OV is set to 1.

Programming Note For mulli and mullw, the low-order 32 bits of the product are the correct 32-bit product for 32-bit mode.

For mulli and mu/Id, the low-order 64 bits of the product are independent of whether the operands are regarded as signed or unsigned 64-bit integers.

For mu/Ii and mullw, the low-order 32 bits of the product are independent of whether the operands are regarded as signed or unsigned 32-bit integers.

Programming Note

The XO-form Multiply instructions may execute faster on some imple-mentations if RB con-tains the operand having the smaller absolute value.

Multiply Low Immediate D-form

mulli RT,RA,SI

[Power mnemonic: muli]

7 I 11 RA product of the operands are placed into register RT.

Both operands and the product are interpreted as signed integers.

Special Registers Altered None

Multiply Low Doubleword XO-form

mulld RT,RA,RB 128-bit product of the operands are placed into register RT.

If OE=l then OV is set to 1 if the product cannot be represented in 64 bits.

Both operands and the product are interpreted as signed integers.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered CRO

so ov

(if Rc=l) (if OE=l)

Multiply Low Word XO-form

[Power mnemonics: muls, muls., mulso, mulso.]

31 I 11 RA

I

¹⁶ RB 64-bit product of the operands is placed into register RT.

If OE=l then OV is set to 1 if the product cannot be represented in 32 bits.

Both operands and the product are interpreted as signed integers.

Special Registers Altered CRO

so ov

Multiply High Doubleword XO-form mulhd 128-bit product of the operands are placed into register RT.

Both operands and the product are interpreted as signed integers.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered

CRO ^(if Rc=l)

Multiply High Word XO-form

mulhw RT,RA,RB

mulhw. RT, RA, RB

31

I

¹¹ RA

I

^{16 RB}

prodo:63 ~ (RAl32:63 x (RBl32:63 RT32:63 ~ prodo,31

RT o: 31 ^{f -} undefined

75

(Rc=O) (Rc=l)

The 32-bit operands are the low-order 32 bits of RA and of RB. The high-order 32 bits of the 64-bit product of the operands are placed into RT 32:63· (RT)o:31 are undefined.

Both operands and the product are interpreted as signed integers.

Special Registers Altered CRO

Multiply High Doubleword Unsigned XO-form mulhdu

mulhdu.

31

RT,RA,RB RT,RA,RB

I 11 RA prodo:l27 ~ (RA) x (RB) RT ^{f -} prod_{0 ,}63

I 16 RB 9

(if Rc=ll

(Rc=O) (Rc=l)

The 64-bit operands are (RA) and (RB). The high-order 64 bits of the 128-bit product of the operands are placed into register RT.

Both operands and the product are interpreted as unsigned integers, except that if Rc=l the first three bits of CR Field 0 are set by signed com-parison of the result to zero.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered

CRO (if Rc=ll

Multiply High Word Unsigned XO-form mulhwu

mulhwu.

31

RT,RA,RB RT,RA,RB

I 11 RA I ¹⁶ RB prodo:63 f-- CRAl32:63 x (RBl32:63 RT32:63 f-- prodo:31

RT o: 3l r undefined

11

(Rc=O) (Rc=l)

The 32-bit operands are the low-order 32 bits of RA and of RB. The high-order 32 bits of the 64-bit product of the operands are placed into RT 32:63· (RT)o:31 are undefined.

Both operands and the product are interpreted as unsigned integers, except that if Re= 1 the first three bits of CR Field 0 are set by signed com-parison of the result to zero.

Special Registers Altered

CRO (if Rc=ll

Programming Note The 64-bit signed remainder of dividing (RA) by (RB) can be computed as follows, except in the case that (RA)

=

-2⁶³ and (RB)

=

-1.

di vd RT. RA, RB II RT - quotient mulld RT,RT,RB

#RT - quotient*divisor subf RT,RT,RA II RT - remainder

Divide Doubleword XO-form

divd RT,RA,RB not supplied as a result.

Both operands and the quotient are interpreted as signed integers. The quotient is the unique signed integer that satisfies

dividend= (quotient x divisor) + r

where 0 ~ r < /divisor/ if the dividend is nonnegative, and -/divisor/ < r ~ 0 if the dividend is negative.

If an attempt is made to perform any of the divisions Ox8000_0000_0000_0000 + -1

<anything> + 0

then the contents of register RT are undefined as are (if Rc=l) the con-tents of the LT, GT, and EQ bits of CR Field 0. In these cases, if OE=l then OV is set to 1.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered CRO

so ov

(if Rc=l) (if OE=l)

Divide Word XO-form 64-bit divisor is the sign-extended value of (RBb2:63· The 64-64-bit quotient is formed. The low-order 32 bits of the 64-bit quotient are placed into RT 32:63· (RT)o:31 are undefined. The remainder is not supplied as a result.

Both operands and the quotient are interpreted as signed integers. The quotient is the unique signed integer that satisfies

dividend= (quotient x divisor)+ r

where 0 $ r < ldivisorl if the dividend is nonnegative, and -ldivisorl < r $ 0 if the dividend is negative.

If an attempt is made to perform any of the divisions Ox8000_0000 + -1 be computed as follows, except in the case that (RA)= -2³¹ and (RB)= -1.

Programming Note The 64-bit unsigned remainder of dividing (RA) by (RB) can be computed as follows.

divdu RT,RA,RB

Divide Doubleword Unsigned XO-form

div du RT,RA,RB not supplied as a result.

Both operands and the quotient are interpreted as unsigned integers, except that if Re= 1 the first three bits of CR Field 0 are set by signed com-parison of the result to zero. The quotient is the unique unsigned integer that satisfies

dividend= (quotient x divisor) + r where 0 ~ r < divisor.

If an attempt is made to perform the division

<anything>+ 0

then the contents of register RT are undefined as are (if Rc=1) the con-tents of the LT, GT, and EQ bits of CR Field 0. In this case, if 0£=1 then OV is set to 1.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered CRO

so ov

(if Rc=l) (if OE=l)

Divide Word Unsigned XO-form 64-bit divisor is the zero-extended value of (RBb2:63· The 64-64-bit quotient is formed. The low-order 32 bits of the 64-bit quotient are placed into RT 32:63· (RT)o:31 are undefined. The remainder is not supplied as a result.

Both operands and the quotient are interpreted as unsigned integers, except that if Re= 1 the first three bits of CR Field 0 are set by signed com-parison of the result to zero. The quotient is the unique unsigned integer that satisfies

dividend= (quotient x divisor) + r where 0 ::; r < divisor.

If an attempt is made to perform the division

<anything> + 0 The 32-bit unsigned remainder of dividing (RA)32:63 by (RBh2:63 can be computed as follows.

divwu RT.RA.RB

Im Dokument BUSl, ~ESS (Seite 116-133)