Fixed-Point Rotate and Shift Instructions

The Fixed-Point Processor performs rotation operations on data from a GPR and returns the result, or a portion of the result, to a GPR.

The rotation operations rotate a 64-bit quantity left by a specified number of bit positions. Bits that exit from position 0 enter at position 63.

Two types of rotation operation are supported.

For the first type, denoted rotate64 or ROTL64, the value rotated is the given 64-bit value. The rotate64 operation is used to rotate a given 64-bit quantity.

For the second type, denoted rotate32 or ROTL3i, the value rotated consists of two copies of bits 32:63 of the given 64-bit value, one copy in bits 0:31 and the other in bits 32:63. The rotate32 operation is used to rotate a given 32-bit quantity.

The Rotate and Shift instructions employ a mask generator. The mask is 64 bits long, and consists of 1-bits from a start bit, mstart, through and including a stop bit, mstop, and 0-bits elsewhere. The values of mstart and mstop range from 0 to 63. If mstart > mstop, the 1-bits wrap around from position 63 to position 0. Thus the mask is formed as follows:

if mstart ~ mstop then maskmstart:mstop = ones maska11 other bits= zeros else

maskmstart:6 3 = ones masko:mstop = ones

mas ka11 other bits = zeros There is no way to specify an all-zero mask.

For instructions that use the rotatq2 operation, the mask start and stop positions are always in the low-order 32 bits of the mask.

The use of the mask is described in following sections.

The Rotate and Shift instructions with Re= 1 set the first three bits of CR field 0 as described in Section 3.3.8, "Other Fixed-Point Instruc-tions," on page 80. Rotate and Shift instructions do not change the OV and SO bits. Rotate and Shift instructions, except algebraic right shifts, do not change the CA bit.

Extended Mnemonics for Rotates and Shifts

The Rotate and Shift instructions, while powerful, can be complicated to code (they have up to five operands). A set of extended mnemonics is

ing the leftmost or rightmost bits of a register, left justifying or right justi-fying an arbitrary field, and performing simple rotates and shifts. Some of these extended mnemonics ::irP ~hown "~ e::o::?.~p!e~ '.'/it!-:. ::!-:.;:: Rctat<:

instructions. See Appendix C, "Assembler Extended Mnemonics," on page 215 for additional extended mnemonics.

Fixed-Point Rotate Instructions

These instructions rotate the contents of a register. The result of the rota-tion is

• inserted into the target register under control of a mask (if a mask bit is 1 the associated bit of the rotated data are placed into the tar-get register, and if the mask bit is 0 the associated bit in the tartar-get register remains unchdnged); or

• ANDed with a mask before being placed into the target register.

The Rotate Left instructions allow right-rotation of the contents of a register to be performed (in concept) by a left-rotation of 64-n, where n is the number of bits by which to rotate right. They allow right-rotation of the contents of the low-order 32 bits of a register to be performed (in concept) by a left-rotation of 32-n, where n is the number of bits by which to rotate right.

Rotate Left Doubleword Immediate then Clear Left MD-form rldicl

The contents of register RS are rotated64 left SH bits. A mask is gener-ated having 1-bits from bit MB through bit 63 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error

Programming Note rldicl can be used to extract an n-bit field that starts at bit position b in register RS, right-justified into register RA (clearing the remaining 64-n bits of RA), by setting SH=b+n and MB=64-n. It can be used to rotate the contents of a register left (right) by n bits by setting SH=n (64-n) and MB=O. It can be used to shift the contents of a register right by n bits by setting 5H=64-n and MB=n. It can be used to clear the high-order n bits of a register by setting SH=O and MB=n.

Extended mnemonics are provided for all of these uses: see Appendix C,

"Assembler Extended Mnemonics," on page 215.

Programming Note rldicr can be used to extract an n-bit field that starts at bit position bin register RS, left-justified into register RA (clearing the remaining 64-n bits of RA), by setting SH=b and ME=n-1. It can be used to rotate the contents of a register left (right) by n bits by setting SH=n (64-n) and ME=63.

It can be used to shift the contents of a register left by n bits by setting SH=n and ME=63-n. It can be used to clear the low-order n bits of a register by setting SH=O and ME=63-n.

Extended mnemonics are provided for all of these uses (some devolve to rldicl): see Appendix C,

"Assembler Extended Mnemonics," on page 215.

handler to be invoked.

Special Registers Altered CRO

Extended Mnemonics:

(if Rc=l)

Examples of extended mnemonics for Rotate Left Doubleword Immedi-ate then Clear Left: Rotate Left Doubleword Immediate then Clear Right MD-form

rldicr

The contents of register RS are rotated64 left SH bits. A mask is gener-ated having 1-bits from bit 0 through bit ME and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered

CRO (if Rc=l)

Extended Mnemonics:

Examples of extended mnemonics for Rotate Left Doubleword Immedi-ate then Clear Ri:<ht:

Extended: Equivalent to:

extldi Rx,Ry,n,b rldicr Rx,Ry,b,n-1

sldi Rx,Ry,n rldicr Rx,Ry,n,63-n

clrrdi Rx,Ry,n rldicr Rx,Ry,0,63-n

Rotate Left Doubleword Immediate then Clear MD-form rldic result is placed into register RA.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered CRO

Extended Mnemonics:

(if Rc=l)

Example of extended mnemonics for Rotate Left Doubleword Immediate then Clear: the high-order b bits of the contents of a register and then shift the result left by n bits by setting

Extended mnemonics are provided for both of these uses (the second devolves to rldicl): see Appendix C, "Assembler Extended Mnemonics,"

on page 215.

Rotate Left Word Immediate then AND with Mask M-form rlwinm

rlwinm.

RA,RS,SH,MB,ME RA,RS,SH,MB,ME [Power mnemonics: rlinm, rlinm.]

21 RS

The contents of register RS are rotated32 left SH bits. A mask is gener-ated having 1-bits from bit MB+32 through bit ME+32 and 0-bits else-where. The rotated data are ANDed with the generated mask and the result is placed into register RA.

Special Registers Altered CRO

Extended Mnemonics:

(if Rc=l)

Examples of extended mnemonics for Rotate Left Word Immediate then AND with Mask:

Extended: Equivalent to:

extlwi Rx,Ry,n,b rlwinm Rx,Ry,b,O,n-1

SrWI Rx,Ry,n rlwinm Rx,Ry,32-n,n,31

clrrwi Rx,Ry,n rlwinm Rx,Ry,0,0,31-n

Rotate Left Doubleword then Clear Left MOS-form

rldcl RA,RS,RB,MB (Rc=O) Let RSL represent the low-order 32 bits of register RS, with the bits numbered from O through 31.

rlwinm can be used to extract an n-bit field that starts at bit position b in RSL, right-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting SH=b+n, MB=32-n, and ME=31. It can be used to extract an n-bit field that starts at bit position b in RSL, left-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting SH=b, MB= 0, and ME=n-1. It can be used to rotate the contents of the low-order 32 bits of a register left (right) by n bits by setting SH=n (32-n), MB=O, and ME=31. It can be used to shift the contents of the low-order 32 bits of a register right by n bits by setting SH=32-n, MB=n, and ME=31. It can be used to clear the high-order b bits of the low-order 32 bits of the contents of a register and then shift the result left by n bits by setting SH=n, MB=b-n and ME=31-n.

It can be used to clear the low-order n bits of the low-order 32 bits of a register by setting SH=O, MB=O, and ME=31-n.

above, the high-order 32 bits of register RA are cleared.

Extended mnemonics are provided for all of these uses: see Appendix C, extract an n-bit field that starts at variable bit position b in register RS, right-justified into register RA (clearing the remaining 64-n bits of RA), by setting

RBsa:63=b+n and MB=64-n. It can be used to rotate the contents of a register left (right) by variable n bits by setting RB58:63=n (64-n) and MB=O.

Extended mnemonics are provided for some of these uses: see Appendix C, "Assembler Extended Mnemonics," on page 215.

Programming Note rider can be used to extract an n-bit field that staits at variable bit position bin register RS, left-justified into register RA (clearing the remaining 64-n bits of RA), by setting RBsa:63=b and ME=n-1. It can be used to rotate the contents of a register left (right) by variable n bits by setting RB58:63=n (64-n) and ME=63.

Extended mnemonics are

The contents of register RS are rotated64 left the number of bits speci-fied by (RB)ss:63· A mask is generated having 1-bits from bit MB through oir 63 anci 0-oits eisewhere. The rotated data are ANDed with the gener-ated mask and the result is placed into register RA.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered CRO

Extended Mnemonics:

(if Rc~l)

Example of extended mnemonics for Rotate Left Doubleword then Clear Left:

Extended:

rotld Rx,Ry,Rz

Equivalent to:

rldcl Rx,Ry,Rz,0 Rotate Left Doubleword then Clear Right MOS-form

rldcr RA,RS,RB,ME (Rc=O)

The contents of register RS are rotated64 left the number of bits speci-fied by (RB)s8:63· A mask is generated having 1-bits from bit 0 through bit ME and 0-bits elsewhere. The rotated data are ANDed with the gener-ated mask and the result is placed into register RA.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered

CRO (if Rc~l)

provided for some of these uses (some devolve to rldcf): see Appendix C,

"Assembler Extended Mnemonics," on page 215.

Programming Note Let RSL represent the low-order 32 bits of register RS, with the bits numbered from O through 31.

rlwnm can be used to extract an n-bit field that starts at variable bit position bin RSL, right-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting RB 59,63=b+n, MB=32-n, and ME=31. It can be used to extract an n-bit field that starts at variable bit position b in RSL, left-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting RBs9:63=b, MB = 0, and ME=n-1. It can be used to rotate the contents of the low-order 32 bits of a register left (right) by variable n bits by setting RBs9:63=n (32-n), MB=O, and ME=31.

For all the uses given above, the high-order 32 bits of register RA are cleared.

Extended mnemonics are provided for some of these uses: see Appendix

Rotate Left Word then AND with Mask

rlwnm RA,RS,RB,MB,ME

rlwnm. RA,RS,RB,MB,ME

[Power mnemonics: rlnm, rlnm.)

I

^{o 23}

¹⁶

^RS

I

^{11 RA}

The contents of register RS are rotated32 left the number of bits speci-fied by (RB)59:63· A mask is generated having 1-bits from bit MB+32 through bit ME+32 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.

Special Registers Altered

Extended: Equivalent to:

rotlw Rx,Ry,Rz rlwnm Rx,Ry,Rz,0,31

Rotate Left Doubleword Immediate then Mask Insert MD-form

rldimi RA,RS,SH,MB

gen-Mnemonics," on page 215.

Programming Note rldimi can be used to insert an n-bit field that is right-justified in register RS into register RA starting at bit position b by setting 5H=64-{b+n) register RA, with the bits numbered from 0 through 31.

rlwimi can be used to insert an n-bit field that is left-justified in the low-order 32 bits of register RS into RAL starting at bit position b by setting 5H=32-b, MB=b, and ME=(b+n)-1. It can be used to insert an n-bit field that is right-justified in the low-order 32 bits of register RS into RAL starting at bit position b by setting SH=32-{b+n), MB=b, and ME=(b+n)-1.

Extended mnemonics are provided for both of these uses: see Appendix C, "Assembler Extended Mnemonics," on page 215.

where. The rotated data are inserted into register RA under control of the generated mask.

T~i:; ili:ii::<"uci:i.::n1 i~ Jc:f.11c:u uuiy fur 64-bir impiementat1ons. Usmg it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered CRO

Extended Mnemonics:

(if Rc=l)

Example of extended mnemonics for Rotate Left Doubleword Immediate then Mask Insert:

Extended: Equivalent to:

insrdi Rx,Ry,n,b rldimi Rx,Ry,64-(b+n),b Rotate Left Word Immediate then Mask Insert M-form rlwimi

rlwimi.

RA,RS,SH,MB,ME RA,RS,SH,MB,ME [Power mnemonics: rlimi, rlimi.]

20 RS 111 RA

The contents of register RS are rotated32 left SH bits. A mask is gener-ated having 1-bits from bit MB+32 through bit ME+32 and 0-bits else-where. The rotated data are inserted into register R,a. under control of the generated mask.

Special Registers Altered

CRO (if Rc=l)

Programming Note Multiple-precision shifts can be programmed as shown in Appendix E.2,

"Multiple-Precision Shifts," on page 256.

Extended Mnemonics:

Example of extended mnemonics for Rotate Left Word Immediate then Mask Insert:

Extended: Equivalent to:

inslwi Rx,Ry,n,b rlwimi Rx,Ry,32-b,b,b+n-1

Fixed-Point Shift Instructions

The instructions in this section perform left and right shifts.

Extended Mnemonics for Shifts

Immediate-form logical (unsigned) shift operations are obtained by speci-fying appropriate masks and shift values for certain Rotate instructions.

A set of extended mnemonics is provided to make coding of such shifts simpler and easier to understand. Some of these are shown as examples with the Rotate instructions. See Appendix C, "Assembler Extended Mnemonics," on page 215 for additional extended mnemonics.

Shift Left Doubleword X-form sld

sld.

31

n f- CRB)5s:63

RA, RS, RB RA,RS,RB

RS

r f- ROT L64 ( (RS) , n) i f (RBl 57 ⁼ 0 then

m f- MASK(O, 63-n) else m ..- 64 0

RA ..- r & m

RA I 16 RB 27

(Rc=O) (Rc=l)

The contents of register RS are shifted left the number of bits specified by (RB)s7:63· Bits shifted out of position 0 are lost. Zeros are supplied to the vacated positions on the right. The result is placed into register RA.

Shift amounts from 64 to 127 give a zero result.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered

(if Rc=l)

Shift Left Word X-form slw

slw.

RA,RS,RB RA,RS,RB [Power mnemonics: sl, sl.]

31 RS

I 11 RA n f- (RBls9:63

r f- ROTL 32 ((RS) 3z:63· n) i f (RB lss = O then

m f- MASK(32, 63-nl else m f- 640

RA f- r & m

I

^{16 RB 24}

(P_c-0) (Rc=l)

The contents of the low-order 32 bits of register RS are shifted left the number of bits specified by (RB)ss:63· Bits shifted out of position 32 are lost. Zeros are supplied to the vacated positions on the right. The 32-bit result is placed into RA32:63· RAo:31 are set to zero. Shift amounts from 32 to 63 give a zero result.

Special Registers Altered CRO

Shift Right Doubleword X-form srd

srd.

31

n f- (RBlss:63

RA,RS,RB RA,RS,RB

RS

I

^{11 RA}

r f- ROTL64((RS), 64-n) if (RB)_{57 =} 0 then

m f- MASK(n, 63) else m f- 64 0

RA f- r & m

I 16 RB 539

(if Rc=l)

(Rc=O) (Rc=l)

The contents of register RS are shifted right the number of bits speci-fied by (RB)57:63. Bits shifted out of position 63 are lost. Zeros are sup-plied to the vacated positions on the left. The result is placed into register RA. Shift amounts from 64 to 127 give a zero result.

This instruction is defined only for 64-bit implementations. Using it on

a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered CRO

Shift Right Word X-form srw

srw.

RA,RS,RB RA,RS,RB [Power mnemonics: sr, sr.]

31 RS

I 11 RA n f - (RB) 59: 63

r f - ROTL 32 ((RSl32:63· 64-n) if (RB) 58 ⁼ 0 then

m f - MASK(n+32, 63) else m f - 64 0

RA f - r ^& m

I ¹⁶ RB 536

(if Rc=l)

(Rc=O) (Rc=l)

The contents of the low-order 32 bits of register RS are shifted right the number of bits specified by (RB)ss:63· Bits shifted out of position 63 are lost. Zeros are supplied to the vacated positions on the left. The 32-bit result is placed into RA32:63· RAo,31 are set to zero. Shift amounts from 32 to 63 give a zero result.

Special Registers Altered

CRO (if Rc=l)

Shift Right Algebraic Doubleword Immediate

The contents of register RS are shifted right SH bits. Bits shifted out of position 63 are lost. Bit 0 of RS is replicated to fill the vacated positions on the left. The result is placed into register RA. CA is set to 1 if (RS) is negative and any 1-bits are shifted out of position 63; otherwise CA is set to 0. A shift amount of zero causes RA to be set equal to (RS), and CA to be set to 0.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered CA

CRO

Shift Right Algebraic Word Immediate X-form sraw1

sraw1.

RA,RS,SH RA,RS,SH [Power mnemonics: srai, srai.]

31 RS

I

¹¹ RA Any Shift Right Algebraic i1-1:>i..1 uLiiu11, fuiiuweci Dy addze, can be used to divide quickly by 2N. The setting of the CA bit by the Shift Right Algebraic instructions is

independent of mode.

The contents of the low-order 32 bits of register RS are shifted right SH bits. Bits shifted out of position 63 are lost. Bit 32 of RS is replicated to fill the vacated positions on the left. The 32-bit result is placed into RA32:63· Bit 32 of RS is replicated to fill RAo:31· CA is set to 1 if the low-order 32 bits of (RS) contain a negative number and any 1-bits are shifted out of position 63; otherwise CA is set to 0. A shift amount of zero causes RA to receive EXTS((RSlJ2:63), and CA to be set to 0.

Special Registers Altered CA

CRO

Shift Right Algebraic Doubleword X-form srad

srad.

31

n (--- (RB) 58: 63

RA,RS,RB RA,RS,RB

RS

I

¹¹ RA

r (--- ROTL64((RS), 64-n) if (RB)57 ⁼ 0 then

m (--- MASK(n, 63) else m (--- 64 0

s (--- (RS) o

RA (--- r&m I (⁶⁴sJ&-.m CA (--- s & ( ( r&-. m h=O)

I 16 RB 794

(if Rc=l)

(Rc=O) (Rc=l)

The contents of register RS are shifted right the number of bits speci-fied by (RB)s7:63· Bits shifted out of position 63 are lost. Bit 0 of RS is replicated to fill the vacated positions on the left. The result is placed into register RA. CA is set to 1 if (RS) is negative and any 1-bits are shifted out of position 63; otherwise CA is set to 0. A shift amount of zero

The contents of register RS are shifted right the number of bits speci-fied by (RB)s7:63· Bits shifted out of position 63 are lost. Bit 0 of RS is replicated to fill the vacated positions on the left. The result is placed into register RA. CA is set to 1 if (RS) is negative and any 1-bits are shifted out of position 63; otherwise CA is set to 0. A shift amount of zero

Im Dokument BUSl, ~ESS (Seite 150-163)