The PowerPC Architecture supports a family of processors that spans a wide range of system and application environments. It also provides a stable base for software, allowing applications that run on one PowerPC processor to run consistently on any other PowerPC processor and well-designed operating systems to be moved from one processor implementa-tion to another by making a few minor changes. These desirable yet seemingly conflicting attributes are achieved by structuring the architec-ture specification into three Books, and relegating all implementation-specific aspects of the architecture to a fourth Book that is unique for each implementation. The first three Books correspond to three levels of the architecture, as follows.
• Book I, User Instruction Set Architecture
This Book describes the registers, instructions, storage model, and exe-cution model that are available to all application programs.
• Book II, Virtual Environment Architecture
This Book describes features of the architecture that permit applica-tion programs to create or modify code, to share data among
pro-grams in a multiprocessing system, and to optimize the performance of storage accesses.
• Book III, Operating Environment Architecture
This Book describes features of the architecture that permit operating systems to allocate and manage storage, to handle errors encountered by application programs, to support I/O devices, and to provide the other services expected of secure, modern, multiprocessor operating systems.
This volume consists of Books I, II, and III. The fourth Book, called Book IV, PowerPC Implementation Features, differs for each implemen-tation and is not included herein.
An important attribute of Books I, II, and III is that they do not con-strain implementations on matters that would not affect software com-patibility. For example, the effects of executing an invalidly coded instruction are not defined and can differ between implementations.
Compilers and assemblers are responsible for generating only correctly coded instructions.
An even more important attribute of these three Books is that they specify the architecture in a manner that is independent of implementa-tion. For example, Book III specifies the rules by which storage addresses are translated from the "effective addresses" generated by a program to the "real addresses" that are used to access storage, including the format of related tables and registers that are needed by the operating system.
However, it does not specify how a processor should accomplish the translation. Thus, it permits translation lookaside buffers (TLBs) to be used, but does not require that they be used and does not specify their organization or contents. Book IV for each processor specifies all such implementation details, and use of the related facilities can be isolated to small portions of the operating system.
All PowerPC processors conform to Book I. The PowerPC processors being developed jointly by Motorola and IBM for the general computer market conform to Books II and III as well. Other implementations may support only a subset of the features described in these two Books. (In effect, such an implementation would have its own private Book II or III.) For example, a processor used as an embedded controller might conform to Books I and II but implement a simpler storage model than the one described in Book III.
Because the features described in Book III are available only to "privi-leged" programs such as operating systems, application binary compati-bility is assured even for processors that implement a different Book III.
The ability to change portions of Book III in the future may prove very
useful, to support new developments in operating system and hardware technology and unforeseen processor requirements.
As used in this volume, the term "PowerPC Architecture" refers gener-ically to the instructions and facilities described in Books I, II, and III.
However, it is important to remember that these Books define three dis-tinct levels of the architecture, and thus three different levels of compati-bility.
Acknowledgements
We would like to acknowledge Keith Diefendorff, Ron Hochsprung, Rich Oehler, and John Sell for providing the technical leadership that made it possible for the group of architects, programmers, and designers from Apple, Motorola, and IBM to produce an architecture that met the goals established by the alliance these companies formed.
Many people contributed to the definition of the architecture, and it is not practical to name each of them here. However, a core group worked long hours over an extended period contributing ideas, evaluating options, debating costs and benefits of each proposal, and working together toward the goal of establishing a competitive architecture for the member companies of the alliance. This group of dedicated professionals included Richard Arndt, Roger Bailey, Al Chang, Barry Dorfman, Greg Grohoski, Randy Groves, Bill Hay, Marty Hopkins, Jim Kahle, Chin-Cheng Kau, Cathy May, Chuck Moore, Bill Moyer, John Muhich, Brett Olsson, John O'Quin, Mark Rogers, Tom Sartorius, Mike Shebanow, Ed Silha, Rick Simpson, Hank Warren, Lynn West, Andy Wottreng, and Mike Yamamura.
Instruction Set Architecture
Chapter 1 Introduction 3
1.1 Overview 3
1.2 Computation Modes 3
1.3 Instruction Mnemonics and Operands 4 1.4 Compatibility with the POWER Architecture 4
1.5 Document Conventions 5
1.6 Processor Overview 11
1.7 Instruction Formats 12
1.8 Classes of Instructions 23
1.9 Forms of Defined Instructions 25
1.10 Exceptions 26
1.11 Storage Addressing 27
Chapter 2 Branch Processor 31
2.1 Branch Processor Overview 31
2.2 Instruction Fetching 31
2.3 Branch Processor Registers 32
2.4 Branch Processor Instructions 35
Chapter 3 Fixed-Point Processor 47
3.1 Fixed-Point Processor Overview 47
3.2 Fixed-Point Processor Registers 47 3.3 Fixed-Point Processor Instructions 49 Chapter4 Floating-Point Processor 133 4.1 Floating-Point Processor Overview 133 4.2 Floating-Point Processor Registers 135
4.3 Floating-Point Data 141
Appendix B Suggested Floating-Point
Models 203
B.1 Floating-Point Round to Single-Precision Model 203 B.2 Floating-Point Convert to Integer Model 209 B.3 Floating-Point Convert from Integer Model 212 Appendix C Assembler Extended
Mnemonics 215
C.1 Symbols 215
C.2 Branch Mnemonics 216
C.3 Condition Register Logical Mnemonics 222
C.4 Subtract Mnemonics 223
C.5 Compare Mnemonics 223
C.6 Trap Mnemonics 225
C.7 Rotate and Shift Mnemonics 227
C.8 Move To/From Special Purpose Register
Mnemonics 230
C.9 Miscellaneous Mnemonics 231
Appendix D Little-Endian Byte Ordering 233
D.1 Byte Ordering 233
D.2 Structure Mapping Examples 234
D.3 PowerPC Byte Ordering 236
D.4 PowerPC Data Storage Addressing in
Little-Endian Mode 240
D.5 PowerPC Instruction Storage Addressing in
Little-Endian Mode 242
D.6 PowerPC Cache Management and Lookaside Buffer Management Instructions in Little-Endian Mode 245 D.7 PowerPC 1/0 in Little-Endian Mode 245
D.8 Origin of Endian 246
Appendix E Programming Examples 249
E.1 Synchronization 249
E.2 Multiple-Precision Shifts 256
E.3 Floating-Point Conversions 259
E.4 Floating-Point Selection 264
Appendix F Cross-Reference for
Changed POWER Mnemonics 267
Instructions
G.2 Newly Privileged Instructions G.3 Reserved Bits in Instructions G.4 Reserved Bits in Registers G.S Alignment Check
G.6 Condition Register
G. 7 Inappropriate use of LK and Re Bits G.8 BO Field
G.9 Branch Conditional to Count Register G.10 System Call
G.11 Fixed-Point Exception Register (XER) G.12 Update Forms of Storage Access G.13 Multiple Register Loads
G.14 Alignment for Load/Store Multiple G.1S Move Assist Instructions
273
G.16 Synchronization 276
G.17 Move To/From SPR 276
G.18 Effects of Exceptions on FPSCR Bits FR and Fl 277 G.19 Floating-Point Store Instructions 278
G.20 Move From FPSCR 278
G.21 Zeroing Bytes in the Data Cache 278 F.22 Floating-Point Load/Store to Direct-Store
Segment 280
G.23 Segment Register Instructions 278
G.24 TLB Entry Invalidation 279
G.2S Floating-Point Interrupts 279
G.26 Timing Facilities 279
G.27 Deleted Instructions 280
G.28 Discontinued Opcodes 282
G.29 POWER2 Compatibility 283
Appendix H New Instructions 287 H.1 New Instructions for All Implementations 287 G.2 New Instructions for 64-Bit Implementations
Only 291
G.3 New Instructions for 32-Bit Implementations
Only 292
Appendix I Illegal Instructions 291 Appendix J Reserved Instructions 293 Appendix K PowerPC Instruction Set Sorted by
Opcode 29S
Appendix L PowerPC Instruction Set Sorted by
Mnemonic 30S
1.1 Overview
This chapter describes computation modes, compatibility with the POWER Architecture, document conventions, a processor overview, instruction formats, storage addressing, and instruction fetching.
1.2 Computation Modes
The PowerPC Architecture allows for the following types of implementa-tion:
• 64-bit implementations, in which all registers except some Special Pur-pose Registers are 64 bits long and effective addresses are 64 bits long.
All 64-bit implementations have two modes of operation: 64-bit mode and 32-bit mode. The mode controls how the effective address is in-terpreted, how status bits are set, and how the Count Register is tested by Branch Conditional instructions. All instructions provided for 64-bit implementations are available in both modes.
• 32-bit implementations, in which all registers except Floating-Point Registers are 32 bits long and effective addresses are 32 bits long.
Instructions defined in this document are provided in both 64-bit implementations and 32-bit implementations unless otherwise stated.
Instructions that are provided only for 64-bit implementations are illegal in 32-bit implementations, and vice versa.