Fixed-Point Load Instructions

The byte, halfword, word, or doubleword in storage addressed by EA is loaded into register RT.

Byte order of PowerPC is Big-Endian by default; see Appendix D, "Lit-tle-Endian Byte Ordering," on page 233 for PowerPC systems operated with Little-Endian byte ordering.

Many of the Load instructions have an "update" form, in which

regis-Compatibility Note For a discussion of POWER compatibility The "la" extended mnemonic permits computing an effective address as a Load or Store instruction would, but loads the address itself into a GPR rather than loading the value that is in storage at that address. This extended mnemonic is described in

"Load Address," on page 232.

Programming Note In some

implementations, the Load Algebraic and Load with Update instructions may have greater latency than other types of Load instructions. Moreover, Load with Update instructions may take longer to execute in some implementations than the corresponding pair of a non-update Load instruction and an Add instruction.

and RA;eRT, the effective address is placed into register RA and the stor-age element (byte, halfword, word, or doubleword) addressed by EA is loaded into RT.

Load Byte and Zero D-form

lbz RT,D(RA)

34 I 11 RA D

i f RA = 0 th en b +-- 0 el s e b +-- C RA l EA +-- b + EXTSCD)

RT +-- ⁵⁶0 11 MEMC EA. 1)

Let the effective address (EA) be the sum (RAIO)+D. The byte in stor-age addressed by EA is loaded into RT 56:63· RT 0:55 are set to 0.

Special Registers Altered None

Load Byte and Zero Indexed X-form

lbzx RT,RA,RB

31 I ¹¹ RA I 16 RB

if RA= O then b +-- O el s e b +-- ( RA) EA +-- b + (RB)

RT+-- ⁵⁶0 II MEMCEA. ll

87

Let the effective address (EA) be the sum (RAIO)+(RB). The byte in storage addressed by EA is loaded into RT56:63· RTo:55 are set to 0.

Special Registers Altered None

Load Byte and Zero with Update D-form

lbzu RT,D(RA)

35 I 11 RA

EA~ (RA) + EXTS(D) RT~ ⁵⁶0 II MEMCEA. l l RA ~ EA

D

Let the effective address (EA) be the sum (RA)+D. The byte in storage addressed by EA is loaded into RT 56:63· RT 0:55 are set to 0.

EA is placed into register RA.

If RA=O or RA=RT, the instruction form is invalid.

Special Registers Altered None

Load Byte and Zero with Update Indexed X-form

lbzux RT,RA,RB

lo

³¹ 16

RT I 11

RA I 16 RB I 21

119

EA ~ (RA) + (RB) RT ~ 560 11 MEM( EA. 1) RA ~ EA

Let the effective address (EA) be the sum (RA)+(RB). The byte in stor-age addressed by EA is loaded into RT 56:63· RT 0:55 are set to 0.

EA is placed into register RA.

If RA=O or RA=RT, the instruction form is invalid.

Special Registers Altered None

Load Halfword and Zero D-form

lhz RT,D(RA)

40

I

^{11 RA D}

i f RA ⁼ 0 then b f- 0 el s e b f- ( RA) EA f- b + EXTS(D)

RT f- 480 II MEM(EA, 2)

Let the effective address (EA) be the sum (RAIO)+D. The halfword in storage addressed by EA is loaded into RT48:63· RTo:47 are set to 0.

Special Registers Altered None

Load Halfword and Zero Indexed X-form

lhzx RT,RA,RB

31 I 11 RA I 16 RB

if RA = 0 then b f- 0

el s e b f- CRA )

EA f- b + (RB)

RT f- 480 11 MEMCEA, 2)

279

Let the effective address (EA) be the sum (RAIO)+(RB). The halfword in storage addressed by EA is loaded into RT48:63· RTo:47 are set to 0.

Special Registers Altered None

Load Halfword and Zero with Update D-form

lhzu RT,D(RA)

I

o 41

16

^RT

I 11

^RA

116

^D

EA ^~ (RA) + EXTS(D) RT ~ 48 0 II MEM(EA, 2) RA ~ EA

Let the effective address (EA) be the sum (RA)+D. The halfword in storage addressed by EA is loaded into RT48:63· RTo:47 are set to 0.

EA is placed into register RA.

If RA=O or RA=RT, the instruction form is invalid.

Special Registers Altered None

Load Halfword and Zero with Update Indexed X-form

lhzux RT,RA,RB

I o 31

16

^RT

111

^RA

116

^RB I

21

³¹¹

EA ~ (RA) + (RB) RT ~ 48 0 II MEM( EA, 2) RA ^~ EA

Let the effective address (EA) be the sum (RA)+(RB). The halfword in storage addressed by EA is loaded into RT48:63· RTo:47 are set to 0.

EA is placed into register RA.

If RA=O or RA=RT, the instruction form is invalid.

Special Registers Altered None

Load Halfword Algebraic D-form

Iha RT,D(RA)

42 I 11 RA D

if RA = 0 then b f--- 0

else b f--- (RA)

EA f--- b + EXTS(D) RT f--- EXTS(MEM(EA, 2))

Let the effective address (EA) be the sum (RAIO)+D. The halfword in storage addressed by EA is loaded into RT48:63· RTo:47 are filled with a copy of bit 0 of the loaded halfword.

Special Registers Altered None

Load Halfword Algebraic Indexed X-form

lhax RT,RA,RB

31

Ill

^RA

^I

^{16 RB}

if RA = 0 then b f--- 0

else b f--- (RA)

EA f--- b + (RB)

RT f--- EXTS(MEM(EA, 2))

343

Let the effective address (EA) be the sum (RAIO)+(RB). The halfword in storage addressed by EA is loaded into RT48:63· RTo:47 are filled with a copy of bit 0 of the loaded halfword.

Special Registers Altered None

Load Halfword Algebraic with Update D-form

lhau RT,D(RA)

43 I 11 RA D

EA f - (RA) + EXTS(D) RT f - EXTS(MEM(EA, 2)) RA ^{f -} EA

Let the effective address (EA) be the sum (RA)+D. The halfword in storage addressed by EA is loaded into RT 48:63· RT 0:4 7 are filled with a copy of bit 0 of the loaded halfword.

EA is placed into register RA.

If RA::O or RA::RT, the instruction form is invalid.

Special Registers Altered None

Load Halfword Algebraic with Update Indexed X-form

lhaux RT,RA,RB

I o 31

16

RT I 11

RA I 16 RB I 21

375

EA f- CRAl + (RB) RT f- EXTS(MEM(EA, 2)) RA f- EA

Let the effective address (EA) be the sum (RA)+(RB). The halfword in storage addressed by EA is loaded into RT48:63· RTo,47 are filled with a copy of bit 0 of the loaded halfword.

EA is placed into register RA.

If RA::O or RA::RT, the instruction form is invalid.

Special Registers Altered None

Load Word and Zero D-form

lwz RT,D(RA)

[Power mnemonic: l]

32 I 11 RA

if RA ~ 0 then b ^{f -} 0 else

EA ^f

-b f- (RA) b + EXTS(D)

D

Let the effective address (EA) be the sum (RAIO)+D. The word in stor-age addressed by EA is loaded into RT32:63· RTo:31 are set to 0.

Special Registers Altered None

Load Word and Zero Indexed X-form

lwzx RT,RA,RB

[Power mnemonic: Ix]

31 I 11 RA _I 16 RB

if RA= 0 then b f - 0 el s e b f - C RA ) EA f - b + <RB l

RT f - 320 11 MEMCEA, 4)

23

Let the effective address (EA) be the sum (RAIO)+(RB). The word in storage addressed by EA is loaded into RT32:63· RTo:31 are set to 0.

Special Registers Altered None

Load Word and Zero with Update D-form

lwzu RT,D(RA)

[Power mnemonic: lu]

c=33.-~16 _RT~l_11 _RA~[

1_6 _ _ _ D _ _

___,J

EA ^{f -} CRA) + EXTS(D) RT f - 320 JI MEMCEA, 4) RA f - EA

Let the effective address (EA) be the sum (RA)+D. The word in storage addressed by EA is loaded into RT32:63· RTo:31 are set to 0.

EA is placed into register RA.

If RA=O or RA=RT, the instruction form is invalid.

Special Registers Altered None

Load Word and Zero with Update Indexed X-form

lwzux RT,RA,RB

[Power mnemonic: lux]

I o

31

16

^{RT I 11 RA I}

16

RB

121

55

EA f - (RA) + (RB) RT f - 320 11 MEM( EA, 4) RA f - EA

Let the effective address (EA) be the sum (RA)+(RB). The word in storage addressed by EA is loaded into RT32:63· RTo:31 are set to 0.

EA is placed into register RA.

If RA=O or RA=RT, the instruction form is invalid.

Special Registers Altered None

Load Word Algebraic OS-form

lwa RT,DS(RA)

58 I ¹¹ RA

if RA~ 0 then b ^{f -} 0 el s e b f - ( RA) EA f - b + EXTS(DSllDbOOl RT ^{f -} EXTS(MEM(EA, 4))

DS

Let the effective address (EA) be the sum (RAIO)+(DSllObOO). The word in storage addressed by EA is loaded into RT 32:63· RT 0:31 are filled with a copy of bit 0 of the loaded word.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered None

Load Word Algebraic Indexed X-form

lwax RT,RA,RB

31 I

11

RA

I 16

RB 341

if RA~ 0 then b <--- 0 el s e b <--- ( RA ) EA<--- b + (RB)

RT<--- EXTS(MEM(EA, 4))

Let the effective address (EA) be the sum (RAIO)+(RB). The word in storage addressed by EA is loaded into RT32:63· RTo:31 are filled with a copy of bit 0 of the loaded word.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered None

Load Word Algebraic with Update Indexed X-form

lwaux RT,RA,RB

I o

31

16

^RT

111

^{RA I}

16

RB _I

21

³⁷³

EA <--- (RA) ⁺ (RB) RT <--- EXTS(MEM(EA, ^{4) )} RA <--- EA

Let the effective address (E.,_A,_) be the sum (RA)+(RB). The word in storage addressed by EA is loaded into RT32:63· RTo:31 are filled with a copy of bit 0 of the loaded word.

EA is placed into register RA.

If RA=O or RA=RT, the instruction form is invalid.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered None

Load Doubleword OS-form

Id RT,DS(RA)

58 I

11

^RA

if RA ⁼ 0 then b r 0

else b r (RA)

EA r b + EXTS (DSllObOO) RT r MEM(EA, 8)

DS

Let the effective address (EA) be the sum (RAIO)+(DSllObOO). The dou-bleword in storage addressed by EA is loaded into RT.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered None

Load Doubleword Indexed X-form

ldx RT,RA,RB

I

^{o 31}

¹⁶

^RT

¹¹¹

^RA

I ¹⁶

^RB

if RA = 0 then b r 0

else b r (RA)

EA r b + (RB) RT r MEM(EA, 8)

I ²¹

²¹

_~~I

Let the effective address (EA) be the sum (RAIO)+(RB). The double-word in storage addressed by EA is loaded into RT.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered None

Load Doubleword with Update OS-form

!du RT,DS(RA)

58 I 11 RA

EA f- (RA) + EXTS<DSiiObOO) RT f- MEM(EA, 8)

RA f- EA

DS

Let the effective address (EA) be the sum (RA)+(DSllObOO). The dou-bleword in storage addressed by EA is loaded into RT.

EA is placed into register RA.

If RA=O or RA=RT, the instruction form is invalid.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered None

Load Doubleword with Update Indexed X-form

ldux RT,RA,RB

31

EA f- ( RA) + ( RB) RT f- MEM(EA, 8) RA f- EA

111

RA

I

¹⁶ RB 53

Let the effective address (EA) be the sum (RA)+(RB). The doubleword in storage addressed by EA is loaded into RT.

EA is placed into register RA.

If RA=O or RA=RT, the instruction form is invalid.

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.

Special Registers Altered None

Im Dokument BUSl, ~ESS (Seite 84-96)