High-temperature CVD processes for crystalline silicon thin-film and wafer solar cells

(1)

for crystalline silicon thin-film and wafer solar cells

Dissertation

zur Erlangung des akademischen Grades Doktor der Naturwissenschaften

(Dr. rer. nat.)

an der Universität Konstanz Fachbereich Physik

vorgelegt von

Evelyn Karin Schmich

Fraunhofer Institut für Solare Energiesysteme Freiburg

2008

Konstanzer Online-Publikations-System (KOPS) URL: http://www.ub.uni-konstanz.de/kops/volltexte/2008/6549/

URN: http://nbn-resolving.de/urn:nbn:de:bsz:352-opus-65498

(2)

Referenten:

Prof. Dr. Gerhard Willeke Prof. Dr. Paul Leiderer

Tag der mündlichen Prüfung: 18.07.2008

(3)

1 Introduction

In the year 2007, a different light was shed on the global potential for renewable energy. For the first time, a global common roadmap for a secure climate future and the wish of a binding deal to reduce at long-term the emissions of green house gases were presented at the United Nations' World Climate Change Conference held in Bali in December [1]. Furthermore, the European Commission has put forward an ambitious target for 20% renewable energy by 2020 in Europe’s overall energy mix [2]. A swift transfer towards renewable energies is necessary to decelerate the climatic change.

The sun is a huge, regenerative and clean energy source; a simple calculation demonstrates the potential of solar energy to satisfy the energy consumption of humans: the incident solar light on earth is approximately 1 kW per m² and thus 130 Million GW of solar energy reach the earth’s land surface. In comparison, the actual global energy consumption is about 10000 times lower [3]. Therefore, only a small fraction of the incoming light needs to be accessible to humans and to be converted to electrical or thermal energy in order to satisfy the human energy consumption. The conversion of solar light into electrical energy can be performed by solar cells.

The high potential of solar cells reached also the industry. The PV production in 2007 was between 3.4GW_P [4] and 4.2 GW_P [5] and a total installation of 12.4 GW_P [6]. Since 2003 the annual growth rate is, on average, more than 50%

[5, 7]. Such an increased interest for solar cells promotes the research for cheaper and more efficient solar cells.

The current industrial solar cell market is mainly based on crystalline silicon (c-Si). In 2007 the market was dominated by single crystal wafers (42%) and multicrystalline (mc) wafers (45%), with smaller shares allotted to silicon ribbons (2.2%) and thin-films, such as CIS (0.5%), CdTe (4.7%) and a-Si:H (5.2%) [5]. The thin-film sector grew by almost 80%, indicating that this technology is gaining an increased acceptance [7]. One reason is that only a small amount of expensive material is used, compared to a standard silicon module in which 50% of the costs are from the silicon wafer [8]. High-purity silicon is very difficult to produce and much effort and many cleaning steps are necessary in order to reach purity levels of better than 1 ppb [9]. The price of

(8)

SEMI¹ quality silicon is between 60 and 200 €/kg and is partly this high due to the actual scarcity of high-quality silicon. It now becomes clear that the costs can be dramatically reduced when using alternative silicon sources independent from the microelectronics or concepts with reduced silicon consumption.

One way to decrease the cost of the solar cells is to use solar grade poly silicon, with purity levels between 0.1 and 1000 ppm [10]. This silicon feedstock also has a cost projection of 15-20 €/kg [10, 11] so alternative technologies to decrease even further the solar cell cost are necessary. For example, silicon losses due to wafering can be avoided when using the direct growth of silicon ribbons (e.g. edge defined film-fed growth (EFG) and ribbon growth on substrates (RGS)).

An alternative approach is the deposition of a high-purity silicon thin-film on a cheap substrate [12]. Low cost substrates such as metallurgical silicon (mg-Si), glass or ceramics can be used. Wafers with epitaxial growth on low-cost silicon substrates are also called epitaxial wafer-equivalents (EpiWE), due to their resemblance to standard wafers. The concept of crystalline silicon thin-film (cSiTF) solar cells can substantially reduce silicon material consumption and has the potential to reach high efficiencies comparable to wafer silicon solar cells.

The deposition of a thin silicon film by high-temperature chemical vapour deposition (CVD) and using a high-throughput reactor would cost below 15

€/m² [13]. Therefore, a module made of crystalline silicon thin-film solar cells with 15% efficiency could costs below 1 €/W_P [13, 14]. Compared to typical a module of multicrystalline solar cells with an actual module cost of 4.7 €/W_P [15], the thin-film approach has a significant cost reduction potential.

Since the early 1960s silicon thin-film solar cell concepts have been investigated [16]. However, due to the evolution of the PV market during the last years, the research was emphasised on this subject and a large variety of concept have been presented.

1Semiconductor Equipment and Materials International is a trade organization and defines, among other activities, the standards specifications in the industry.

(9)

mg, mc or Cz p⁺ Si substrate p epitaxial base

p⁺ epitaxial BSF n⁺ emitter

porous intermediate layer texture

Figure 1-1: Scheme of an epitaxial wafer-equivalent.

Outline of this thesis

This thesis deals with the optimisation of crystalline silicon thin-film solar cells grown by high-temperature atmospheric pressure chemical vapour deposition on silicon substrates. Through the concept of the epitaxial wafer-equivalent the sticking points were defined and examined extensively. In-situ processes were developed in order to minimise the process cost of the cell. Figure 1-1 shows the concept pursued in this thesis, with the following emphasis: the influence of the substrate quality, the optical confinement by intermediate porous silicon layer and front side texture, the optimisation of the epitaxial films for the use of BSF, base and emitter.

Chapter 2 presents a short overview of crystalline silicon thin-film solar cell approaches. Firstly, the advantages of crystalline silicon thin-film concepts are pointed out. Concepts using low and high-temperature silicon deposition are presented with the emphasis on the direct epitaxial deposition at high temperature. The concepts pursued at Fraunhofer ISE, i.e. the epitaxial and recrystallised wafer-equivalents are described.

Chapter 3 presents an introduction to the chemical vapour deposition (CVD) of silicon at atmospheric pressure (APCVD) - the basic method used in this work. The reaction kinetics and the doping incorporation for this CVD technique are presented and compared to the experimental data gained in the lab-type CVD reactors. Furthermore, the deposition concept, the CVD reactors and process control at Fraunhofer ISE are explained in detail.

In Chapter 4, the efforts made in the last years to improve the efficiencies of the epitaxial wafer-equivalent solar cells are summarised. A short overview of the simulation tool and the applied solar cell processes is given. The cell

(10)

parameters are then examined in terms of their dependence on the substrates features. The cleaning, the block position and gettering of the substrate are investigated. Thereafter, the growth of the epitaxial layer by a different precursor is experimentally examined. The back surface field (BSF) and base are optimised by simulations and experimental results are shown. The influence of the epitaxial BSF, base doping, lifetime and thickness is investigated in detail.

One main focus of this thesis, the application of silicon epitaxy for the emitter formation, is shown in Chapter 5. The advantages of the emitter deposition and restrictions due to the CVD reactors are presented. The deposition process, which was elaborated in this work, is then described in detail with emphasis on the doping profile and solar cell results. Solar cells of wafers with epitaxial emitters of both doping types are presented and finally, the concept is applied to p-type crystalline silicon thin-film solar cells on Czochralski and multicrystalline substrates. Furthermore, simulations results are shown and the recombination within the space charge region is investigated. The application to industrial relevant screen-printing technique is evaluated and first solar cells are presented.

The application of HCl etching of silicon for solar cells is presented in Chapter 6. Firstly, the surface kinetics and surface morphology is introduced.

HCl gas etching is a subject of research to perform in-situ processes for optical confinement, i.e. porous intermediate layers and texturing. Detailed process descriptions and properties for the use as internal reflector are presented.

Additionally, the gettering effect of HCl etching is elaborated. The performance was firstly tested on substrates with relatively low-impurity level. The influence of the HCl getting was detected by lifetime measurements. The process was then applied on metallurgical substrates and characterised by mass spectrometry. A microscopic analysis and first solar cells are presented.

(11)

2 The concepts of crystalline silicon thin- film solar cells

This chapter introduces the most common concepts and the advantages of crystalline silicon thin-film solar cells. The low and high-temperature approaches, as well as the transfer techniques, are explained. The emphasis will remain on the concepts followed at Fraunhofer ISE, which are the epitaxial and recrystallised wafer-equivalents.

2.1

Introduction

As already mentioned in Chapter 1, the silicon thin-film concepts were mainly introduced to reduce the cost of solar cells. Thin-films are, by definition, materials created by random nucleation and growth processes on a substrate [14]. The thickness of thin-films may vary from a few nanometres to tens of micrometers [14], usually less than 50 µm [17] for solar cell applications. As silicon is an indirect semiconductor, thick layers or improved light trapping are needed in order to reach efficiencies comparable to wafer solar cells. With optimum optical confinement and taking into account radiative and Auger recombination, an efficiency up to 25% is theoretically possible for a 10 µm cell or 15% for a 0.5 µm thick cell [17]. Traditionally, concepts of crystalline silicon thin-film (cSiTF) solar cells are divided into low and high-temperature approaches, depending on the temperature of the silicon deposition and maximum toleration of the substrate. The transfer technique is an exception to this classification, as the silicon layer is grown at high temperature but the solar cell substrate withstands only low temperatures.

2.2

Advantages of crystalline silicon thin-film solar cells

The realisation of silicon thin-film solar cells profits from both thin-film and silicon wafer characteristics. The main advantages are listed below, with the focus on the epitaxial wafer-equivalent, which is described in the high- temperature section.

Advantages of wafer silicon:

- Silicon is a non-toxic and abundant material.

- Silicon has high and stable lifetimes.

(12)

- Due to the importance of silicon in the microelectronic industry, there is much knowledge about the properties and handling of silicon.

- A large PV industry dealing with silicon wafers is already established and much process knowledge specific to solar cells can be transferred.

- The solar cell process of the epitaxial wafer-equivalent is similar to the state- of-the-art process in the PV industry and consequently there is a low acceptance threshold of using this new concept in the PV industry. The investments and risks are minimised [14].

- A high process yield of cSiTF solar cell production is probable because the production quality monitoring tools can be transferred from the wafer production [14].

Advantages of thin-films:

- Thin-film solar cells have a low material consumption of high-purity silicon.

- Low purity substrates can be used, reducing the total costs of the solar cells.

- Fast and large area deposition (depending on the technique) can be used, resulting in high-throughput production.

- It may also be possible to simplify some solar cell processes. In-situ processes, such as emitter epitaxy and HCl cleaning can be applied in the wafer-equivalent approach.

2.3

Low-temperature approach

Crystalline silicon thin-film solar cells grown at low temperatures have the advantage that a large variety of substrates are available. Materials such as float glass, high-temperature boron-silicate and soda lime glass, plastic films and even steel can be used as the growth temperature is limited to 600°C.

Contamination problems in the deposited silicon film are reduced because diffusion is negligible at low temperatures. The disadvantage is that the process temperature is limited by the substrates and a very low growth rate results.

Typical growth rates are between 3 and 10 nm/min and this is the limiting step for the industrialisation of microcrystalline silicon [18]. Depending on the growth technique, the deposited silicon films have different grain sizes, which are classified as shown e.g. in Figure 2-1. When the silicon film is deposited below 400°C by PECVD, nanocrystalline or microcrystalline structures are obtained, whereas polycrystalline structures are formed when the deposition is made by thermal CVD at temperatures above 600°C [18]. Larger grains usually result in higher efficiencies thus often the film is recrystallised to improve the

(13)

grain structure. However, as the substrate is not heat resistant in this approach, low-temperature recrystallisation must be used e.g. by rapid thermal annealing, solid-phase, laser, e-beam and aluminium induced recrystallisation [19]. An advantage of low-temperature deposition is that hydrogen is incorporated in the silicon layer during the deposition. It thereby passivates defects and grain boundaries [18], but in comparison to large crystal structures, many grain boundaries are still active and have high recombination rates. Another disadvantage of the concept is that the solar cell process has to be adapted, e.g.

for the emitter diffusion.

1 nm

Grain size

1 m

1 µm 1 mm 1 cm

100 nm

Nano- Micro- Poly- Multi-

Mono- crystalline

1 nm

Grain size

1 m

1 µm 1 mm 1 cm

100 nm

Nano- Micro- Poly- Multi-

Mono- crystalline

Figure 2-1: A common classification of crystal structures according to grain sizes.

The first fabrication of µc-Si:H using PECVD was performed in 1979 [18], but micro-crystalline silicon thin-film solar cells were not considered feasible at first due to poor quality. In 1994, the research group at the Institute for Microelectronics at the University of Neuchâtel presented a single junction solar cell with an efficiency over 7% [18]. Nowadays, the best cell efficiencies on glass superstrates have values above 12% [20]. Increased efficiencies up to 15.0% are reached [21] when using a micromorph tandem structure, i.e. the combination of a microcrystalline bottom cell with an amorphous silicon top cell, and an efficient light trapping. In 2004, Kaneka Corporation presented a module with an aperture efficiency of 13.4% [22].

2.4

High-temperature approach

The high-temperature deposition of silicon is mainly accomplished by two methods, liquid phase epitaxy or chemical vapour deposition (CVD), the latter technique is explained in detail chapter 3. Silicon deposition performed at temperatures above 1000°C typically produces good crystal quality. On substrates with a similar lattice match to silicon, epitaxial² growth occurs and results in poly-, multi- or even monocrystalline silicon films, depending on the

2 Epitaxy is deviated from ‘epi’ and ‘taxis’, which means in greek ‘upon’ and ‘ordered’, respectively. Epitaxy denotes the growth of crystals of a material on the crystal base of another material, such that the crystalline substrates of both materials have the same structural orientation [23].

(14)

substrate structure (Figure 2-1). Despite the high temperature, if a foreign material substrate is used, a polycrystalline film is deposited and grain enlargement becomes necessary to reach acceptable efficiencies. As a rule of thumb for good efficiencies, the diffusion length in cSiTF solar cells should be more than 2 times longer that the thickness of the layer. Due to the fact that the substrate is heat-resistant, high-temperature recrystallisation techniques can be applied, e.g. rapid-thermal annealing, laser, liquid-phase or zone-melting recrystallisation. However, the requirements for the substrate are quite demanding and there are less suitable substrates available compared to the low- temperature approach. Furthermore, the purity of the substrate has to be high enough so that only few impurities can diffuse into the active layer during the deposition. For substrates with a high number of impurities, an intermediate layer is necessary to act as a diffusion barrier. Three main concepts within the high-temperature approach are presented in this section:

- the epitaxial thin-film silicon solar cell on a low cost silicon substrate;

- the recrystallised thin-film silicon solar cell on foreign, conductive and non- conductive substrates;

- and the lift-off thin-film silicon solar cell, where the silicon substrate is reused.

2.4.1 Epitaxial wafer-equivalents

The simplest form of a crystalline silicon thin-film (cSiTF) solar cell is an epitaxial active layer deposited on a highly-doped inactive silicon substrate (Figure 2-2-A). Due to its resemblance to a silicon wafer solar cell it is also called the epitaxial wafer-equivalent (EpiWE). Standard industrial solar cell processes can be applied to this wafer-equivalent.

CSiTF solar cells were first fabricated in the 1970s. Chu et al. presented epitaxial silicon thin-films deposited on purified and uni-directionally solidified mg-Si substrates. They reached efficiencies up to 9.7% measured under an AM1 spectrum [24]. Despite this effort, little progress was made with EpiWEs until years later. In the 1990s, high-efficiencies were investigated with a best result from a 45 µm thick epitaxy layer on an Fz substrate with an ion-implanted SiO₂ layer beneath the surface. With this sophisticated SIMOX³ approach and a high- efficiency solar cell process, a 19.2% cell efficiency was reached [25].

3 SIMOX: Separation by IMplanted OXygen.

(15)

Nowadays, more cost-effective substrates and solar cell processes are used. An attractive option to reduce the substrate costs while keeping the impurity level of the substrate low is the recycling of waste silicon. Such materials are highly- doped reclaimed wafers from the microelectronics industry or ‘tops and tails’

from Czochralski-grown silicon, which are cast to multicrystalline silicon (off- spec cast mc). More abundant, but also more impure substrates are metallurgical grade silicon (mg-Si) or up-graded mg-Si (umg-Si). The impurities diffuse through the material easily at high temperatures and it is difficult to develop a process that prevents the formation of recombination centres.

As the substrate and the deposited layer in the epitaxial Si solar cell have the same refractive index, no internal reflection occurs at this interface. In order to introduce optical confinement, an intermediate layer with a different refractive index must be identified that also allows good quality crystal growth. This could be achieved by using e.g. porous silicon, of which the porosity and therefore the refractive index can be adjusted [26, 27]. The advantage is that epitaxy is possible on porous silicon without sacrificing the quality of the epitaxial layer.

This method was also part of this thesis project and is described in more detail in Section 6.3. Another option is to deposit a perforated SiO2 layer, which is then overgrown by the epitxay. A selective epitaxial growth through a pattern of openings with liquid phase epitaxy was already developed by [28]. The oxide layer has a perfect refractive index for this purpose and acts additionally as a diffusion barrier.

At present, research with optimised solar cell concepts is underway. E.g. the emitter wrap-through concept is known to reduce the grip shadowing [29]. A concept combining the advantages of the wafer-equivalent approach and the emitter wrap-through concept is currently under investigation [30].

n⁺emitter 0.4 - 1 µm

low cost ceramic

substrate 270 µm p epitaxial base 20 µm n⁺emitter 0.4 - 1 µm

low cost p⁺Si

substrate 270 µm p epitaxial base 20 µm

A B C

p⁺epitaxial BSF 2 µm p⁺zone molted BSF 2 µm

intermediate layer 0.2 µm p⁺zone molted BSF 2 µm

intermediate layer 0.2 µm n⁺emitter 0.4 - 1 µm

low cost ceramic

low cost p⁺Si

substrate 270 µm p epitaxial base 20 µm

A B C

p⁺epitaxial BSF 2 µm p⁺zone molted BSF 2 µm

intermediate layer 0.2 µm p⁺zone molted BSF 2 µm

intermediate layer 0.2 µm

Figure 2-2: Thin-film concepts pursued at Fraunhofer ISE: Epitaxial wafer-equivalent (A), Laser-fired rear access (LFA) (B), recrystallised wafer-equivalent on ceramics (C).

(16)

2.4.2 Zone-melted crystalline films

By zone-melting recrystallisation (ZMR), microcrystalline silicon films are melted and cooled in a controlled manner so that the grain size is enlarged to over 10 mm². A long, narrow silicon strip is melted and this liquid zone is scanned across the sample. Thereby, elongated grains of up to 10 cm in length and several millimetres in width are formed [31, 32]. The dislocation density varies widely with crystal orientation [24, 32] and much effort has been invested into achieving large and homogeneous recrystallisations [33].

A new concept called laser-fired rear access (LFA) is currently under development at Fraunhofer ISE. A scheme of these concepts are shown in Figure 2-2-B [34]. On a low-cost and impure silicon substrate, an SiO2 diffusion barrier is deposited and subsequently a silicon layer. The microcrystalline silicon is then zone-melted. A subsequent laser processing creates holes, which penetrate the insulating SiO2 layer. The holes are filled up by an epitaxially deposited base, establishing the connection to the rear side contact (hence the name). This approach combines the advantages of an intermediate SiO2 layer (light trapping and diffusion barrier) with a simple two-sided cell metallisation process. Recently, efficiencies up to 8.4% have been reached at Fraunhofer ISE [34]. Mitsubishi electric corporation presented a 16.5% efficient cell with an SiO₂ intermediate layer and zone-melted film, but more complex cell concept [32]. This proves the potential of this concept.

When using foreign substrates, such as ceramic or graphite, a recrystallisation of the microcrystalline silicon film becomes necessary. On non-conductive substrates, sophisticated cell structures are applied, such as front side contacts.

These solar cell processes are too complex for a low-cost industrial application and therefore efforts are channelled to the development of conductive substrates and intermediate layers [35]. Figure 2-2-C shows the scheme of a cSiTF solar cell on a ceramic substrate with two-sided contacts, an SiC intermediate layer and ZMR recrystallisation. Efficiencies up to 7.2% were reached so far [35].

2.4.3 Transfer techniques

A compromise between high-temperature epitaxial deposition and low cost substrates can be reached with transfer techniques. A high-quality cSiTF is deposited on a host substrate by epitaxy. The emitter and front contact formation are done while the cSiTF is still attached to the substrate and only after completion of the front-side cell structure the cSiTF is lifted-off and transferred

(17)

to a low-cost substrate. The host substrate can be electrochemically pre-etched to form a highly porous silicon layer (PSI). The porous structure of the layer changes during thermal annealing such that large voids are formed and separation is easily possible. On top of this layer a layer of low porosity is etched so that an epilayer of good quality can be grown. The subsequent solar cell process can be simplified, e.g. by autodiffusion of the emitter when using a highly-doped n-type substrate [36]. The cSiTF is separated mechanically and glued to a textured glass superstrate for mechanical protection. The host- substrate can be reused several times; however, the quality of the epitaxial layer worsens [28].

Another transfer technique is the Epilift concept, where the epitaxy is grown by LPE on a monocrystalline substrate with a mesh-like SiO2 layer. The cSiTF has then a waffle-grid structure, which can be contacted using an interdigitated grid. Efficiencies up to 13% have been reached [37].

2.5

Summary

Silicon is a non-toxic, abundant material for which much process knowledge from the microelectronics and solar cell industries can be transferred. Crystalline silicon thin-film solar cells combine the advantages offered by the well- established silicon wafer industry with the advantages of thin-film concepts, such as low material consumption of high-purity silicon and low-cost substrates.

Depending on the process temperature, different substrates are required. For low growth-temperatures cheap substrates such as glass and plastic films can be used. High growth-temperatures need thermally stable substrates, such as ceramics or low-cost silicon. Microcrystalline silicon thin-film solar cells show low conversion efficiencies and recrystallisation methods to enlarge the grains are necessary.

At Fraunhofer ISE two main concepts are pursued: the epitaxial and the recrystallised wafer-equivalents. The simplest approach of crystalline thin-film solar cells is the direct deposition of an epitaxial layer on a low-cost substrate.

Optical confinement is necessary and is accomplished with reflective intermediate layers. Highest efficiencies of 19.2% for epitaxial wafer- equivalents with an ion-implanted SiO₂ layer were reached. Nowadays, more cost-effective approaches are followed, including epitaxial deposition on metallurgical silicon or layer transfer techniques.

(18)

(19)

3 Silicon deposition by Chemical Vapour Deposition (CVD)

As a result of the invention of the bipolar transistor by Bardeen, Brattain and Shockley in 1947 and therefore the necessity of abrupt junctions in silicon, the Chemical vapour deposition (CVD) became the key silicon deposition process for microelectronic production. This chapter introduces the basic techniques for silicon deposition and then focuses on thermal atmospheric pressure CVD, our technique of choice.

The reaction kinetics and the doping incorporation for this CVD technique are introduced. Furthermore, the deposition concept and an overview of the CVD reactors at Fraunhofer ISE are presented. A brief description of the process control in the lab-type reactors concludes this chapter.

3.1

Silicon deposition techniques

Today, a large variety of silicon deposition techniques are available. The spread of different methods can be simplified by classifying them according to the silicon source. Physical Vapour Deposition (PVD) is a technique where thermal or e-beam evaporation first transfers solid silicon into gas phase and the gaseous silicon compounds are then deposited on a substrate. When this occurs in a high vacuum the method is referred to as Molecular Beam Epitaxy (MBE). Liquid Phase Epitaxy (LPE) is a method using a silicon-saturated metal solvent. When the silicon substrate is introduced into the super-saturated liquid at temperatures between 700°C and 900°C, epitaxial growth occurs on the surface with a growth rate up to 1 µm/min [14]. Laboratory type solar cells show good performance [38], but industrial application is challenging as uniform topology over large areas is very difficult with LPE [14, 38].

Another very common deposition technique is Chemical Vapour Deposition (CVD), where a solid film is deposited from a gaseous phase via a chemical reaction. The technique is further classified according to the decomposition from the gaseous phase to the reaction educts. Plasma Enhanced CVD (PECVD) relies on the formation of excited species by the plasma which lower the activation energy required for the dissociation of the precursor gas [14, 38]. The

(20)

plasma is often produced by radio frequency. An alternative method is the Hot- Wire CVD, where a silicon source is decomposed by a catalyst, often a tungsten or tantalum wire. In thermal CVD, the gas dissociation is achieved using only heat, either in the gas or at the substrate surface. Thermal CVD is then divided into different pressure regimes with appropriately various temperatures.

Reduced pressure (RPCVD) operates at pressures between 10³-10⁴ Pa, whereas low pressure (LPCVD) operates at about 10-100 Pa and ultra-high vacuum CVD (UHV-CVD) at 10^-1-10^-3Pa. CVD reactors operating at atmospheric pressure (APCVD) (10⁵Pa) need higher temperatures (950-1250°C) for epitaxy processes than reactors using lower pressure regimes. High-temperature CVD deposition is our technique of choice. It has the advantages of very high deposition rates and growth at atmospheric pressure which simplifies the process procedure. APCVD reactors are commonly used in microelectronics and the chemistry is therefore well understood. The gas-handling, waste-gas treatment and process chemistry are state-of-the-art.

3.2

Principle of thermal atmospheric pressure CVD

The most common CVD processes for silicon epitaxy are based on the hydrogen reduction of chlorosilane. In this thesis the focus lies on CVD deposition with Trichlorosilane (TCS) or Silicontetrachloride (STC) as precursor. Figure 3-1 shows schematically the individual process steps that take place during the deposition: The mass transport of the main gas flow into the deposition zone (A), the gas phase reactions (B), the mass transport of the precursors to the growth surface (C), the adsorption of the precursor to the growth surface (D), the surface diffusion to the growth sites (E), the incorporation of the silicon to the growing film (F), the desorption of the byproducts of the surface reactions (G) and the mass transport of the byproducts into the main gas flow (H) [39].

The type of gas flow, laminar or turbulent, is an important factor for the homogeneity of a deposited layer. The Reynolds number determines the behaviour of the gas depending on the reactor geometry, the gas velocity, the gas density and the gas viscosity. In [39-41] more detailed analyses of the fluid- dynamics in a horizontal CVD reactor are given.

In the next section the reactions kinetics, the resulting growth rate and the chemical yield are briefly described with emphasis on the doping incorporation.

More detailed descriptions can be found in [23, 39, 42-45], among others.

(21)

B A

Substrate Main gas flow

E

H

C D F G

Figure 3-1: Schematic of the partial processes during CVD [39].

3.2.1 Reaction kinetics for Trichlorosilane and Silicontetrachloride A simplified model of silicon deposition from trichlorosilane (TCS) and silicontetrachloride (STC) is presented by Habuka [44] and by Narusawa [46].

Table 3-1 summarises some of the reactions on the silicon growth surface using TCS or STC as precursor, corresponding to the schematic in Figure 3-1.

Gas phase reactions − It was found that the concentration of SiCl2 is lower than that of TCS at the silicon surface [46]. Calculations performed show that at temperatures above 1100°C for any Cl/H ratio, SiCl2 is the dominating silicon species in the gas phase for both precursor types [44, 47, 48]. The STC and TCS quantities in the gas phase decrease with increasing temperature. The reactions (1) and (5) in Table 3-1 occur at Point B in Figure 3-1.

Chemisorption − Reactions (1) and (5) can also take place at point C in Figure 3-1, where the SiHCl₃ is chemisorbed and SiCl₂ is adsorbed. The adsorbed SiCl₂ is denoted by an asterisk. In the model proposed by Habuka et al.

[44], the gas phase reactions are not taken into account because the thermal decomposition of TCS is assumed to be negligible. They conclude that the chemisorbed *SiCl₂ is the dominant species for the silicon growth and that the surface is covered with *SiCl₂. The species in the gas phase and the elemental processes of the epitaxial growth are stable across a wide temperature range.

Decomposition of *SiCl2 − After adsorption, *SiCl₂ is decomposed by hydrogen at the growth surface according to equation (2). The remaining silicon diffuses to a site where incorporation is more favourable. On a plateau region the silicon atoms can only form two bonds to the crystal so they diffuse further along the ledge to a kink site, where an energetically lower binding occurs [41].

The silicon is then incorporated into the crystal.

Desorption and etching − (3) and (7) are competing reactions to the decomposition of *SiCl₂ and results in the desorption of *SiCl₂. For a high yield,

(22)

the rate of *SiCl₂ desorption should be much smaller than that of the chemisorption or silicon etching. Impurity atoms on the surface may react with gaseous species (especially HCl), removing the impurity locally and resulting in a pit. Impurities on the surface may also react with chlorosilanes, in which case the growth is accelerated and results in a hillock on the surface [23].

The total reactions can be described by equation (4) for TCS and equation (6) for STC.

Table 3-1: Reaction kinetics of silicon deposition with TCS, STC and silicon etching.

Process Reaction Point in

Figure 3-1 Gas-phase reaction /

Chemisorption of SiHCl3

↑ +

→ SiCl HCl

SiHCl₃ ^* ₂ (3-1) B, D

Decomposition of ^*SiCl2 ^*SiCl₂+H₂ →Si+2HCl↑ (3-2) D, F Desorption

↑

→

↑

→ +

2

* 2

3

* 2

SiCl SiCl

SiHCl HCl

SiCl (3-3) G

Deposition with TCS

Total reaction SiHCl₃+H₂ →Si+3HCl↑ (3-4) Gas-phase reaction /

Chemisorption of SiCl4

↑ +

↔

+H SiHCl HCl

SiCl₄ ₂ ₃ (3-5) B, D

Chemisorption, Decomposition and Desorption analogue to TCS D, F, G Deposition

with STC

Total reaction SiCl₄+H₂ →Si+4HCl↑ (3-6)

Etching Si⁺nHCl^→SiCl_n ^↑⁺₂ⁿH₂^↑ (3-7)

3.2.2 Growth rate

The growth rate is mainly determined by the temperature, which is shown in Figure 3-2. For low temperatures the kinetics of the surface reaction limit the deposition rate and the growth rate is described by the Arrhenius function as follows:

T) k Aexp(- E rate

growth

B

= A , (3-8)

where A is a pre-exponential factor, E_A is the activation energy, k_B is Boltzmann’s constant and T is the temperature. However, above a certain limit the surface reaction is faster than the rate at which the reactant species reach the surface. Therefore, at high temperatures the deposition rate is limited by the amount of reactants. The deposition rate increases only slightly with temperature and the process is mass-transport limited.

(23)

0.70 0.75 0.80 0.85 0.90 1

1100 1050 1000 950 900

4 3 2

surface reaction limited mass transport

limited

Slope = -E_a/k

Growth Rate [µm/min]

10³/T [°K]

T [°C]

Figure 3-2: Arrhenius plot of the growth rate. At low temperatures the kinetics of the surface reactions limit the deposition rate. At high temperatures the reaction occurs fast and the growth rate is limited by the mass transport.

3.2.3 Chemical yield

The chemical yield refers to the efficiency to convert silicon from the initial gas phase into solid silicon. The initial Si/Cl ratio compared to the exhaust (final) Si/Cl ratio under equilibrium conditions denotes the yield of the silicon deposition or etching. The chemical yield is therefore defined by:

initial final

Si Si Cl

Cl Si

) / (

) / 1− (

η = . (3-9)

The initial Si/Cl ratio depends on the silicon precursor and is 0.33 for TCS and 0.25 for STC. If the final Si/Cl ratio exceeds these values then etching occurred during the process, otherwise deposition. In thermal equilibrium the chemical yield can be calculated by the partial pressures of the silicon and chlorine containing species at a given temperature and Cl/H ratio. The lower the Cl/H ratio the larger is the chemical yield at a given temperature. Increasing the temperature results in higher conversion efficiency due to the enhanced reactivity [47].

3.2.4 Dopant incorporation

The dopant incorporation was investigated in detail by [43, 49, 50] for phosphorus and [49-51] for boron, amongst others. In general, dopant incorporation is described similarly to the silicon growth and depends also on the thermal transport and reaction kinetics shown in Figure 3-1. The incorporation can be modelled by the following equation:

(24)

1 K 0 for p

rate)p growth (T,

K 10 5

C _eff

Si dopant 22 eff

dopant 0

0

≤

⋅

= , (3-10)

where C_dopant is the dopant concentration in the silicon layer, K_eff the effective segregation coefficient from the gas phase to solid silicon and p_0dopant and p_0Si the partial pressures of the dopant containing gas and silicon precursor, respectively [43]. For a complete incorporation of all atoms reaching the surface Keff is equal to 1.

3.2.4.1 Boron incorporation

A common p-type dopant source for many materials and deposition techniques is diborane (B2H6). In APCVD it has the advantage that gas phase doping is easily controlled, as diborane can be diluted in hydrogen [23]. Monoatomic boron in the gas phase is negligible, no species such as B2 or B4 are present and mainly gaseous subhydrides such as BH3 exist at high temperatures. Therefore, a good boron incorporation is possible with a low diborane gas flow [49]. The equation describing the reaction kinetics at the silicon surface is as follows [51]:

2 3

6

2H 2BH 2B 3H

B → → + (3-11)

The desorption of boron atoms from the silicon surface is negligible for small diborane vapour pressures. Competitive chemical reactions between boron incorporation and silicon growth are assumed to exist, resulting in a K_eff lower than 1. Consequently, the incorporated carrier concentration decreases for increasing silicon growth rates [51].

1100 1150 1200 1250 1300 10¹⁷

10¹⁸

B₂H₆ RTCVD100 B₂H₆ from [23]

Boron concentration [cm-3 ]

Temperature [°C]

Figure 3-3: Boron incorporation depending on the growth temperature [23, 43, 50].

(25)

Dependence on the temperature - Another interesting point is that the boron concentration increases with increasing temperature. This occurs because the segregation coefficient (Keff) depends on the deposition temperature [43, 52].

Figure 3-3 shows experimental data from Herring [23] and from the RTCVD100 lab-type reactor at ISE for a diborane concentration of 1.2 ppm and STC as precursor.

Dependence on the diborane gas flow - The carrier concentration of the boron in epitaxial silicon has a linear relationship to the B2H6 concentration in the process gas [51] and is shown experimentally in Figure 3-4. Experimental data from the literature is compared with values from both RTCVD reactors at ISE (see Sections 3.3.2 and 3.3.3) for STC and TCS precursors. The incorporation of boron remains linear up to a concentration of 1x10²⁰cm^-3, but decreases after a peak value near a diborane concentration of 500 ppm [49]. The solubility limit of boron at 1200°C in silicon is about 5x10²⁰ cm^-3 [53], but such high values were not experimentally reported in the literature nor measured at ISE. The reason for the decrease at higher diborane partial pressures is that boron-containing species begin to condense and do not contribute to doping of the epitaxial layer [23]. This reduction could not be observed for the data from ISE. In general, the carrier density deviates by more than one order of magnitude from the literature data to the ISE experiments for the same precursor. Table 3-2 shows the incorporation of boron at 0.1 ppm B₂H₆ for the different processes. Two effects are primarily responsible: the purity of the gas in terms of oxygen and water content and the amount of chlorine. For phosphorus doping the concentrations are too small to have any influence, but for boron doping, the effect of the impurities cannot be neglected [43]. The following reaction takes place in the presence of water:

2 2

2

3 2H O BHO 3H

BH + ↔ + . (3-12)

The boron bound to water is then not incorporated into the epitaxial layer and the total incorporation is thereby lowered for higher oxygen backgrounds. The oxygen content in the commercial reactors is about 0.5-1 ppm [23, 43], whereas it is higher (6 ppm to 20 ppm) in the reactors at ISE (Table 3-2).

Analogous results are found to be dependent on the HCl content in the gas, i.e. Cl/H ratios:

2 3

3 3HCl BCl 3H

BH + ↔ + . (3-13)

(26)

The formation of BCl₃ decreases the free boron content [43]. It is assumed that Rai-Choudhury [49, 54], as well as Habuka [51], used commercial reactors with very low Cl/H ratios between 0.01-0.05. In contrast, the CVD reactors at ISE have Cl/H ratios of 0.1 and 0.75 for the RTCVD160 and RTCVD100, respectively. The amount of chlorine is therefore higher for the RTCVDs, repressing the incorporation of boron. The lower doping for TCS as compared to STC in the RTCVD100 can be similarly explained. Furthermore, in the equilibrium calculations it is assumed that the amount of injected gases are the same as on the surface [43], but the mass transport differs for different reactor types and the calculations are not always applicable. In addition, the inserted gas is diluted with hydrogen gas due to the geometries of the RTCVD reactors.

10^-4 10^-3 10^-2 10^-1 10⁰ 10¹ 10² 10³ 10¹⁴

10¹⁵ 10¹⁶ 10¹⁷ 10¹⁸ 10¹⁹ 10²⁰

Rai-Choudhury (STC, 1230°C) Habuka (TCS, 950°C) RTCVD160 (TCS, 1170°C) RTCVD100 (TCS, 1220°C) RTCVD100 (STC, 1200°C)

Carrier density [cm-3 ]

Diborane [ppm]

Figure 3-4: Boron concentration depending on diborane concentration [49, 51].

Table 3-2: Boron incorporation at 0.1 ppm B2H6 corresponding to Figure 3-4.

Temp [°C]

O2 background [ppm]

Cl/H ratio

Incorporation at 0.1 ppm B2H6

[cm^-3]

Reference / reactor

950 0.5 – 1 [43] 0.01-0.05 1.2x10¹⁸ Habuka [51]

1190 6 0.1 1.2x10¹⁷ RTCVD160

Deposition with TCS

1220 20 0.75 4.0x10¹⁶ RTCVD100

1230 0.5 – 1 [43] 0.01-0.05 3.0x10¹⁹ Rai-Choudhury [49]

Deposition

with STC 1200 20 0.1 3.2x10¹⁷ RTCVD100

(27)

3.2.4.2 Phosphorus incorporation

With the exception of heavy doping dependence, the results of n-type doping are similar to the p-type doping [49]. But in contrast to boron, the phosphorus incorporation has a stronger temperature dependence and is better incorporated at lower temperatures. This can be explained, as phosphorus tends extremely to out-diffuse [55]. The following observations are well described in [43] and [41].

They are summarised here and are highlighted with experimental results from the larger lab-type reactor at Fraunhofer ISE.

0.1 1 10

10¹⁸ 10¹⁹

1150°C 1070°C

1230°C

P concentration [cm-3 ]

Growth rate [µm/min]

1100 1150 1200 1250 1300 10¹⁷

10¹⁸

P concentration [cm-3 ]

Temperature [°C]

Figure 3-5. Phosphorus incorporation versus growth rate at three temperatures [43].

Figure 3-6: Phosphorus incorpora- tion depending on the growth temperature [23, 43, 50]:

Dependence of the growth rate and temperature – Figure 3-5 shows the phosphorus incorporation depending of the growth rate and temperature (data from [43]). The higher the temperature, the higher the out-diffusion of phosphorus, which inhibits a high incorporation of phosphorus at any growth rate (Figure 3-6). At low temperatures an increase of the growth rate results in a higher phosphorus concentration. The reason is that a high concentration of the gaseous phosphorus is present at the silicon surface and the out-diffusion of the incorporated phosphous is slower than the growth process. With further increase of the growth rates the phophorus incorporation decreases at all temperatures since all phosphorus atoms are incorporated. Therefore, the partial pressure near the surface decreases and no equilibrium between the phosphorus in the solid and the vapour is present [56]. In general, phosphorus doping tends to lower the silicon growth rate by competition for surface sites [45].

Dependence on the phosphine gas flow – Figure 3-7 shows a double logarithmic plot of the phosphorus incorporation depending on the injected phosphine concentration. Three different regimes are observed, where the slope

(28)

changes from 1 at low and intermediate PH₃ input pressures, to ½ and even ¼ at high input pressures. The first change in slope can be explained by a change in the composition of the gas phase in contact with the surface, the second change is connected to a transition from intrinsic to extrinsic growth conditions. For all partial pressures the incorporation of phosphorus is assumed to occur only with monoatomic phosphorus.

At low PH3 partial pressures mainly PH3 and PH2 are present in the gas phase:

3 2

0

3 PH PH

PH p p

p = + (3-14)

The composition of the gas changes when it comes into contact with the surface and the following reactions occur:

. H P PH

and H P

PH ₂

2 3 3

2

2 ↔ + ↔ + (3-15)

The partial pressure of phosphine is directly proportional to the partial pressure of the incorporated phosphorus. Therefore, a slope of 1 results in the double logarithmic plot.

) log(const.

) log(p 1

) log(p p

const.

p 3 Si

0

3 P PH P

PH = × ⇒ = × + _(3-16)

At higher PH3 partial pressures, mostly P2 is present in the gas phase:

p 2

0

3 P

PH = × (3-17)

The diphosphorus decomposes to atomic phosphorus at the surface:

P 2

P₂ ↔ × (3-18)

The partial pressure of phosphine is therefore proportional to the power of two of the phosphorus partial pressure. This results in a slope of ½ in the log-log plot:

) log(p )

log(p p

const.

p ⁰

3 0

3 2 PH

1 2 P

P

PH = × ⇒ = × (3-19)

For moderate doping concentration the incorporated phosphorus is ionised at growth temperature. However, at temperatures above 1130°C the intrinsic concentrations for electrons and holes are in the order of 10¹⁹ and 10²⁰ cm^-3, respectively. As long as the phosphorus concentration is low, the electron concentration is determined by the intrinsic concentration and the ionised phosphorus concentration is proportional to the phosphine partial pressure.

When the phosphorus concentration is larger than the intrinsic concentration, the number of electrons is determined by the number of ionised phosphorus atoms.

(29)

The ionised phosphorus concentration is then proportional to the square root of the phosphorus partial pressure:

2 1

P

Si p

]

[P⁺ ∝ . (3-20)

Taking into account the limitation by the P₂ regime, the amount of incorporated ionised phosphorus is proportional to ¼ of the PH₃ partial pressure. Table 3-3 summarises the three regimes. The experimental data corresponds nicely to the theoretical model within the measurement error. The transition from slope ½ to

¼ is expected at 6x10¹⁹cm^-3 and at 1230°C.

Table 3-3: Phosphorus incorporation depending on the PH3 partial pressure.

0

PH3

Si p

]

[P⁺ ∝ for low p⁰_PH₃

2 1 0

3) p ( ]

[P⁺ _Si∝ _PH for high ⁰

PH3

p

4 1 0

3) p ( ]

[P⁺ _Si ∝ _PH for very high ⁰

PH3

p

0.001

0.01 0.1 1 10 100

1000 10¹⁶

10¹⁷ 10¹⁸ 10¹⁹ 10²⁰

Bloem (1130°C) Bloem (1230°C) Aug 05 May 07 Dec 07 Feb 08

Carrier (P+ ) density [cm-3 ]

PH₃ [ppm]

Figure 3-7: Carrier density versus phosphine gas flow injected in the RTCVD160 at 1170°C. Data points from [43] are shown for reference.

3.3

Deposition concept and reactors at Fraunhofer ISE

APCVD reactor designs are explained in much detail in books such as [23, 45, 57] and others. The reactors are generally grouped by the wall temperature (hot and cold wall), the method of heating (resistive, inductive and optical) and their geometry. The most common geometries of reactors are horizontal, barrel, true vertical and pancake reactors. All reactors have in common that they are quite sophisticated yet have a low gas yield. The thickness homogeneity required for microelectronic applications is much severer than for solar cells, where it seems

(30)

that 10% uniformity is sufficient [14]. The crucial point of a CVD system for solar cells is a low-cost reactor with maximum gas conversion and high throughput. The silicon layers needed for EpiWE are quite thick in comparison to typical silicon layers for microelectronic devices. Therefore, a high growth rate is necessary to avoid excessive deposition times [14]. In order to increase the efficiencies in terms of gas yield, throughput and apparatus complexity, a new reactor design was developed at Fraunhofer ISE [58]. Two lab-type reactors and one prototype industrial CVD reactor are currently used at Fraunhofer ISE using this special deposition principle. Their main characteristics are presented showing a brief history of the up-scaling in size and throughput of the reactors.

3.3.1 Deposition principle

The idea is to inject the process gas between the samples, so that the silicon is only deposited on the wafers. Figure 3-8 shows a schematic view of the larger lab-type CVD reactor at Fraunhofer ISE (RTCVD160). The process gas is injected into an inner reaction chamber, whose left and right walls are formed by the samples themselves. The quartz carrier seals the top and bottom walls (not shown). Additionally, the inner volume is surrounded by the quartz tube, which is purged with hydrogen. Therefore, only a little parasitic deposition occurs and the reactor design can be simplified. No complex side wall cooling or specific wafer heating is necessary. The reactor can be heated by halogen lamps or by resistance heating, which are situated on the sides of the quartz tube.

The thickness homogeneity perpendicular to the gas flow on the samples is achieved by different gas injection systems. A small over pressure can be built up with shutters, which force the gas to homogenise in the vertical direction. In contrast to the over pressure, a diffusing shower can disperse the laminar gas flow in the same direction. Alternatively, several injection lines situated in the vertical direction can be used. In addition, a depletion of the silicon precursor gas in the gas flow direction occurs as the reaction kinetics are very fast at these temperatures. In order to level the inhomogeneity in the gas flow direction a continuous deposition is performed by moving the samples in or against the gas flow direction.

(31)

Figure 3-8: Deposition principle of the lab-type reactor RTCVD160.

Figure 3-9: The RTCVD160 during a process.

3.3.2 RTCVD100

The RTCVD100 is the first generation CVD reactor at Fraunhofer ISE with the deposition principle as described above [48, 58]. The ‘100’ in the name signifies the diameter of the reactor quartz tube⁴, which is 100 mm. The wafer carrier is relatively simple as the wafers are placed horizontally and are stacked between quartz rods. Lower and upper wafer rows are therefore formed, separated by two quartz slats on the side and quartz sheets with holes for the gas injection and exhaust at the front and at the end of the inner reaction chamber. The reactor has only one row of halogen lamps situated above the quartz tube so only one row of wafers can be used for silicon deposition with an optimised temperature profile.

This results in a homogeneous silicon deposition zone of only 10 x 5 cm². The CVD processes are usually run at high Cl/H ratios of 0.75 [47] with growth rates between 6 and 10 µm/min. The resultant gas conversion yield is approximately 15%, which can be increased for lower Cl/H ratios. The RTCVD100 is the

‘workhorse’ of the CVD laboratory and has now been running for more than 10 years. This tool has proven that quite a simple reactor and process achieve sufficiently high quality and homogeneous silicon layers for solar cell purposes.

Many depositions for solar cells and etching experiments presented in Chapter 4 and 6 were performed in this reactor.

4 The same applies to the RTCVD160, where the reactor tube has a diameter of 160 mm.

High-temperature CVD processes for crystalline silicon thin-film and wafer solar cells

for crystalline silicon thin-film and wafer solar cells

Dissertation

Evelyn Karin Schmich

Table of contents

1 Introduction

2 The concepts of crystalline silicon thin- film solar cells

2.1

2.2

2.3

2.4

A B C

A B C

2.5

3 Silicon deposition by Chemical Vapour Deposition (CVD)

3.1

3.2

3.3