Epitaxial layer quality

The crystallographic quality of epitaxial layers grown on pores was examined by Normarski microscopy. Figure 6-21 shows the large number of stacking faults and bunch formation on 5 minutes (A) and 3 minutes (B) pre-etched surfaces with subsequent in-situ epitaxy. The 5 minutes etched substrates reveal a higher stacking fault density than on a 3 minutes pre-etched silicon surface. The high number of stacking faults in the active base layer on a 5 minutes etched sample would result in lower cell efficiencies. In contrast, 3 minutes pre-etched wafers may be suitable for the fabrication of solar cells. Compared to the epitaxy on an untreated wafer (C) with an etch pit density of less than 1x10⁴ EP/cm², both samples have an increased etch pit density of around 3x10⁵ EP/cm². For one part, this could occur from different gas flow properties compared to the

standard epitaxy in this reactor, which is optimised for a silicon wafer covered reaction chamber instead of quartz. Furthermore, it is known that epitaxial growth on rough surfaces leads to increased defect densities.

Figure 6-22 shows micrographs of the epitxial layer on HCl-etched mc substrates. Depending on the orientation of the surface, different kinds of defects can be seen. The number of the stacking faults on a <100> orientated grain is comparable to the amount of stacking faults on the <100> monocrystalline surface. The influence of a slower growth rate of 1 µm/min compared to 5-7 µm/min showed no improvement in crystal quality, even though it is reported that a lower deposition rate at growth start results in higher open circuit voltages VOC due to better crystal quality [158].

100 µm

100 µm 100 µm100 µm 100 µm100 µm

Figure 6-21: Top view of epitaxial layers grown on Cz substrates with 5 minutes (A), 3 minutes (B) and without (C) previous etching at 1000°C with 20% HCl concentration.

100 µm 100 µm

Figure 6-22: Top view of epitaxial layers grown on different grains of mc substrates with 3 minutes previous etching at 1000°C with 20% HCl concentration.

A B C

6.3.4 Solar cells

The impact of the pores on the cell properties is difficult to determine solely from measurements of the optical properties. Therefore, crystalline silicon thin-film solar cells on Cz substrates were fabricated in order to gain information about the influence on electrical properties. As the calculations of internal reflection gave no useful information, the four parameters with the highest pore densities were chosen. The applied solar cell process differs from the one described in Section 4.1.2, namely by the etching before epitaxy and the incorporation of a plasma texture after the base deposition, which is used to ensure an optimal optical confinement.

Table 6-2 shows the average values of the cell parameters. These values should be compared to cells without porous layer (e.g. HC513 in Table 5-5).

Firstly, it is noticeable that a shorter annealing does not equal a difference in efficiency. All fill factors have values above 79%, even though a higher deviation is found for the 20% etched samples at 1000°C. Secondly, the reference sample has an open circuit voltage VOC of 30 mV higher than the pre-etched samples. Corresponding etch pit density measurements of the HCl-pre-etched samples show high values above 1x10⁶ EP/cm², whereas etch pit densities of epitaxial layers on polished surfaces are about 1x10⁴ EP/cm². However, despite the very high etch pit densities and therefore lower epitaxial quality, acceptable open circuit voltages can be obtained for thin-films grown on rough surfaces.

All samples etched at 1000°C show 10 mV higher open circuit voltages compared to the samples etched at 950°C. This cannot be explained by a lower etch pit density, as they are similar for both processes.

Due to the optical confinement, more carriers should be absorbed into the active layer and therefore the short circuit current density J_SC should be increased. In contrast to the reference sample, a decrease of more than 1 mA/cm² (etched at 1000°C) and 3 mA/cm² (etched at 950°C) for the mean short circuit current density is found. Internal quantum efficiency measurements clearly show no improvement of carrier collection at long wavelengths (Figure 6-23). Instead, a decrease at short wavelength is noticeable, which may be caused by a lowered crystal quality and surface passivation.

Dark I-V parameters show increased dark saturation current densities J₀₂ of 1x10^-7 A/cm² and lowered shunt resistances R_Sh (Figure 6-24). These parameters indicate an increased recombination in the space charge region and shunts,

which is in good agreement with the high defect density found in the epitaxial layers. It is assumed that a slight increase in J_SC due to reflected light is compensated due to the lower crystal quality and recombination at the pores. To counteract the recombination at defects and pores, a hydrogen passivation should be performed. It may be possible that the effect of HCl-etched porous silicon is beneficial on low-cost mc substrates rather than on Cz, because the epitaxial quality is already low.

Recapitulating, the process at 1000°C with 10% HCl concentration for 3 minutes results in the highest pore density and best efficiencies up to 14.6%.

However, no gain in efficiency compared to reference cells could be achieved and no beneficial optical confinement is found.

Table 6-2: Cell parameters for epitaxial wafer-equivalents with 3 minutes HCl-etched porous intermediate layer.

400 500 600 700 800 900 1000 1100 0

Figure 6-23: Internal quantum efficiency of crystalline silicon thin-film solar cells with porous intermediate layer made by HCl etching.

Figure 6-24: Dark I-V measurement of an epitaxial wafer-equivalent solar cell etched before epitaxy with 20%

HCl concentration for 3 minutes at 1000°C.