Epitaxial growth

To get reasonable cell efficiencies in the region of 10%, the epitaxial layer should result in the lowest possible defect density. Therefore, the crystal quality of the epitaxial growth on pre-etched metallurgical surfaces was examined.

Firstly, epitaxy on CP etched samples without pre-gettering by HCl gas was investigated. Figure 6-34 shows micrographs of silicon surfaces after 8 minutes epitaxial deposition. An increased nucleation is found around the grain boundaries, as is shown in the SEM micrographs. Furthermore, some grains show a preferential facet formation (Figure 6-35-A) and a growth of whiskers is found on the surfaces (Figure 6-35-B). However, in total the surface is relatively smooth and only a few whiskers are noticeable.

1 cm

100 µm 100 µm

Figure 6-34: Normarski (left) and SEM (middle and right) micrographs of metallurgical surfaces with epitaxial layer.

100 µm ^{1 00 µ m}

Figure 6-35: SEM micrographs of epitaxial layers on metallurgical surfaces showing preferential facet formation on a grain (A), whisker growth (B).

A B

0 2 4 6 8 10 12 14

0 1 2

3 Si Au

Au Au

Counts [a.u.]

Binding energy [keV]

Figure 6-36: SEM micrograph and corresponding EDX measurement of ‘wires’ on a metallurgical substrate with subsequent epitaxial growth.

Epitaxial layers were then deposited on substrates gettered with 2% HCl concentration at 1300°C for 20 min. In order to minimise the impurity amount in the epitaxial layer, a second short gettering step after the layer growth was performed. The gettering was performed at the epitaxial growth temperature of 1220°C with 2% HCl concentration for 5 minutes. About 5 µm of the deposited silicon was then removed.

The silicon deposition on HCl-gettered substrates resulted in an increased growth of whiskers, as shown in Figure 6-36-A. The corresponding EDX measurement shows that gold is the impurity that leads to the whisker growth (Figure 6-36-B). The growth of the whiskers can be explained by the vapour-liquid-solid (VLS) mechanism with gold as catalyst. It is known from literature that gold/silicon droplets catalyse the one-directional growth by CVD [174-176].

This VLS mechanism is the most prominent growth technique known today for the growth of nanowires [174]. In a typical VLS process, the gaseous reactants are dissolved into liquid droplets of a catalyst metal. These liquid droplets enhance the nucleation and growth of single-crystalline rods and wires. The liquid droplet serves as a masking which induces the one-dimensional growth [174]. As shown in Table 6-3, the boiling points of some metallic halides are relatively high (e.g. at 1300°C for CrCl3) and some elements, such as gold, start to melt at 1065°C [169]. In contrast to the ungettered substrates, the HCl-gettered substrates with subsequent epitaxy show a higher density of whiskers.

Due to the high-temperature treatment before the epitaxy, impurities diffuse out of large clusters and many small clusters are present on the surface. A subsequent silicon deposition nucleates then preferentially at those precipitations.

Especially after HCl gettering, the epitaxial layer, many whiskers and spikes are visible on the surface. Figure 6-37 shows SEM micrographs of the HCl-gettered epitaxial surfaces. Some clusters and many different whisker types are

A B

noticeable. The whiskers show shapes from round to pointed, but all whiskers have similar heights and widths about 50 µm and 20 µm, respectively. The growth of micrometer-sized whiskers from SiCl4 in the presence of iron or zinc was already reported [177]. The reduction of volatile halides leads to the growth of silicon or even metallic whiskers. The growth of some crystallographic planes gets suppressed if the concentration of certain adsorbed species (e.g. SiCl, FeCl^-, or HCl) exceeds a critical value. These planes form the side faces of the whisker [177]. Whiskers grow only when a local super-saturation exists, which is the case if the partial pressure of the chlorosilanes is high. Indeed, the experiments were performed in the RTCVD100 at a high Cl/H ratio of 0.75. A decreased impurity concentration at the surface should result in better layer qualities.

500 µm 30 µm

300 µm

Figure 6-37: SEM micrographs of HCl-etched epitaxial layers on HCl-gettered metallurgical substrates.

6.6.4 Solar cells

Parallel to the microscopic investigation of epitaxial growth, the electrical properties of solar cells fabricated of those layers on gettered and ungettered substrates were characterised. The gettering of the mg-Si substrate was performed at 1300°C for 20 minutes. Epitaxial layers of 3 µm p⁺-type and approximately 17 µm p-typed doping were deposited. After the deposition some of the wafers were gettered at 1220°C for 5 minutes. Furthermore, references EpiWE solar cells on Cz substrates were fabricated. The solar cell process

described in Section 4.1.2 was used with an additional hydrogen passivation by RPHP before the AR coating.

Table 6-4 shows the mean values and best cell results for the different processes after RPHP and AR coating. Additionally, a reference EpiWE cell on a relatively clean highly-doped mc substrate is shown (OC-09-192). The hydrogen passivation increased the open circuit voltages similarly for all cell types of nearly 30 mV. Nevertheless, the open circuit voltages VOC are below 550 mV, indicating a low quality of the crystalline silicon layer. The EpiWEs on gettered substrates show lower open circuit voltages than on untreated substrates. This may be caused by an increased growth of whiskers, as described in Section 6.6.3 above. The short circuit current density JSC of all cells on mg substrates is about 9 mA/cm² lower than EpiWE on highly-doped mc. All fill factors are below 70% and are lower for the cells with gettering processes. The gettering processes were probably too short to extract all impurities and in contrary long high-temperature processes dissolve more the impurities in the silicon. Furthermore, the fill factors of the reference Cz wafers were affected, probably due to out-diffusion of impurities from the mg substrates during the POCl₃ diffusion. All this indicates that major problems are present in these devices. Nevertheless, the best cell on ungettered substrate reached 7.4% cell efficiency.

Table 6-4: Crystalline silicon thin-film solar cells on metallurgical substrates after ARC.

Dark I-V curves were measured to determine the major problems. Figure 6-38 shows the dark I-V curves of one EpiWE on an mg substrate as well as the reference EpiWE on highly-doped mc. It is noticeable that the series resistances and the dark saturation current densities J₀₁ are not mainly limiting the solar cell

performance. However, even the best EpiWE cells on mg have low shunt resistances Rsh of less than 1000 Ωcm² and increased dark saturation current densities J02 of about 1x10^-6 A/cm². As shown in the microscopic investigations, many defects and impurity clusters are visible on the surfaces. SiC or metallic filaments may penetrate through the epitaxial layer and thus create parallel pn-junctions [121]. The high amount of impurities within the epitaxial layer implies that many traps within the band gap of silicon exist, reducing the bulk lifetime.

Figure 6-39 shows the internal quantum efficiency of an EpiWE on mg substrate. The carrier collection in the bulk is quite low, due to a low lifetime and high surface recombination velocities at the interfaces. Impurity diffusion from the substrate decreases the lifetime in the epitaxial layer. Additionally, inhomogeneous diffusion lengths decreasing towards the grain boundaries were reported and are probably in the range of 7-13 µm [24].

0.0 0.2 0.4 0.6 0.8

Voltage [V] ^{400 600 800 1000 1200}

0

Figure 6-38: Dark I-V curves of epitaxial wafer-equivalents on metallurgical (points) and off-spec (squares) mc silicon substrates.

Figure 6-39: Internal quantum efficiency of an epitaxial wafer-equivalent on a metallurgical substrate (231A).

6.7

Summary

This chapter showed the several applications of HCl gas etching of crystalline silicon. The surface morphology depends strongly on the process temperature and input HCl concentration. Rough surfaces are etched at temperatures between 900 and 1100°C for any HCl concentration. Processes with high diffuse reflectance are found. Applications of such rough surfaces are e.g. structures for optical confinement in epitaxial wafer-equivalents. The etched structures were investigated as front-side texturing. However, the electrical properties show high

surface recombination velocities. As the etched surfaces show pores after annealing, the application as porous intermediate layer for internal reflection was investigated. Pore densities up to 10⁴ pores/mm² are found, however subsequent epitaxial layers show increased etch pit densities. The porosity and thickness of the porous layer seem still to be too low for internal optical confinement and no gain in the short circuit current density is shown. The creation of a porous layer and the subsequent silicon deposition was successfully demonstrated on monocrystalline and multicrystalline wafers.

A purification of the substrate wafer prior to the epitaxial deposition could be performed in-situ with HCl gas. The gettering of the substrates was investigated on lowly contaminated multicrystalline and metallurgical silicon wafers.

Lifetime measurements were performed, showing clearly the gettering effect by HCl gas. High temperatures dissolve the impurity clusters. HCl gettering could not improve the lifetime in the time range studied. However, gettering at 850°C with HCl concentrations between 5 and 16% shows a clear decrease of the total interstitial iron concentration of more than two orders of magnitudes. Lifetimes as high as the reference wafers gettered with phosphorus could be reached.

On metallurgical silicon, the gettering effect of gaseous HCl is more difficult to detect, as direct measurement of carrier lifetimes is difficult. However, by neutron activation analysis, a slight decrease of the impurity concentrations was detected. Microscopic examinations show that surface clusters are preferentially etched by HCl gettering, resulting in holes in the wafers. Gettering at high temperatures was performed without creation of deep holes. Epitaxial growth on the metallurgical silicon shows an increased growth of whiskers and spikes, as well as wires induced by the presence of the metals. Nevertheless, crystalline silicon thin-film solar cells were fabricated on metallurgical substrates with efficiencies up to 7.4%.

7 ^Summary

In this thesis, novel in-situ CVD processes have been investigated that promise to decrease the costs and increase cell efficiencies at the same time. The central approach is the epitaxial wafer-equivalent cell structure, consisting of an epitaxial layer deposited on a low-cost silicon substrate. This epitaxial wafer-equivalent (EpiWE) is then processed using a standard solar cell process. The main goal of this thesis project was to improve the quality and the electrical properties of the deposited films for a future industrial-type application of the crystalline silicon thin-film solar cells. Two major aspects were considered: the silicon deposition with adapted doping profiles and the functional HCl etching for optical confinement and substrate gettering.

Special attention was paid to improving the efficiencies of the crystalline silicon thin-film solar cells with conventional emitters made by POCl₃ diffusion.

The doping level of the base has a major impact on the efficiency and optimum constant doping levels between 6x10¹⁶ and 1x10¹⁷ cm^-3 were determined. This differs slightly from conventional wafer solar cells, which have usually values between 1x10¹⁶ and 3x10¹⁶ cm^-3. Simulations showed that the influence of positive drift fields in the base is relevant for low minority carrier lifetimes and no light confinement. It was found that an epitaxial BSF decreases the short circuit current density when the substrate lifetime is higher than 0.1 µs. For substrates with shorter lifetimes or high interface recombination rates, however, a BSF is essential to hinder the minority carriers from diffusing into the substrate, where they are likely to recombine. From comparisons with simulation results, carrier lifetimes between 1 and 5 µs for epitaxial base layers on Cz substrates have been identified. Epitaxial layers with high base lifetimes showed a large gain in short circuit current density for thicker bases. By applying these optimisations, efficiencies of crystalline silicon thin-film solar cells up to 16.1% on Cz and 14.5% on mc substrates were achieved.

One main focus of this thesis was the application of silicon epitaxy for the emitter formation. This can either be performed ex-situ for wafer cells or in-situ for crystalline silicon thin-film solar cells. Emitter formation by epitaxial growth has many advantages; the most important are the in-situ process for the epitaxial wafer-equivalents, the fast process realisation and the possibility to design the emitter profile as desired. The performance of the emitters was first tested on wafers. Boron-doped emitters were grown on n-type wafers and resulted in

efficiencies up to 15.9%. However, a high surface recombination velocity was observed and better passivation layers than SiO₂ are still required. In contrast, the passivation of SiO2 on n+-type surfaces is excellent and the quality of the epitaxial emitter could be investigated.

A highly innovative process for emitter formation was established in this work, where a blue sensitive emitter can be easily prepared. In order to prevent the phosphorus from out-diffusing from the epitaxial emitter layer, the wafers are cooled in a PH3/H2 atmosphere. This not only prevents the out-diffusion but also increases the doping concentration at the surface. This is advantageous as high surface concentrations are necessary for most metallisation methods in order to achieve low contact resistances. EpiWE solar cells with photolithographic grid definition and evaporated contacts showed efficiencies up to 15.2% on highly-doped Cz substrates and small area. Even on large area cells on Cz material, an efficiency of 14.9% with a high open circuit voltage of 655 mV and a fill factor of 79.9% was achieved, exceeding the values of the reference sample with a 120 Ω/sq. POCl3 emitter. Furthermore, efficiencies up to 13.6% were reached on highly-doped multicrystalline substrates. It was found that the fill factors of the multicrystalline cells with epitaxial emitters are partly limited due to the inhomogeneous growth of the emitter on different grain orientations. Furthermore, simulation results and dark saturation current densities lower than 1x10^-8 Ωcm² indicate that the recombination within the space charge region is even lower than on corresponding POCl₃ diffused crystalline silicon thin-film solar cells. The growth of an in-situ epitaxial emitter can substitute the conventional POCl₃ emitter for the crystalline silicon thin-film solar cells.

Screen-printed metallisations, which are widely used in the PV industry, require high surface doping concentrations to achieve a low contact resistance.

The combination of screen-printed contacts and epitaxial emitters was performed for the very first time within this work. It was found that a good contact is possible on surfaces with phosphorus concentration of approximately 1x10²⁰ cm^-3, when the cells were fired two times. Efficiencies up to 12.1% were reached on highly-doped multicrystalline substrates, with a high 78.2% fill factor and nearly 620 mV open circuit voltage. These results are similar to POCl₃ diffused cells. Epitaxial emitters have a high potential since the doping profile can be considerably improved compared with industrial-type emitters.

The second main topic of the thesis was the application of functional in-situ HCl etching of silicon for solar cells. Depending on the process parameters, rough surfaces could be etched independent on the grain orientation. The resulting texture showed a predominant diffuse reflectance. Structures such as front-side texturing were investigated, however the electrical properties showed still high surface recombination velocities. After annealing of the rough surfaces, pores of 1-5 µm were created in the substrate. By adjustment of the process parameters pore densities up to 10⁴ pores/mm² were obtained. The porous intermediate layer was investigated for internal reflection, but it has not yet shown a clear gain in the short circuit current density. However, the implementation of a porous layer into the epitaxial wafer-equivalent by simply HCl gas etching prior to the epitaxy, was successfully demonstrated for the first time.

HCl gas additionally reacts with impurities to form highly-volatile chlorides.

The advantage is obvious, as impurities in the substrate could be extracted before the epitaxial deposition. The gettering effect of gaseous HCl was applied to lowly-contaminated multicrystalline and higher contaminated metallurgical silicon wafers. Measurements showed a clear increase in the wafer lifetime by the HCl gettering at a temperature of 850°C. The total interstitial iron concentration could be decreased by more than two orders of magnitudes compared to annealed samples. Lifetimes as high as in reference phosphorus gettered wafers were achieved. On metallurgical silicon, neutron activation analysis also showed a decrease up to 70% of the impurity concentrations. These are the first results presented so far about the gettering effect of hot HCl gas diluted in hydrogen for solar cell application. Gettering at high temperatures was performed successfully with subsequent epitaxial deposition. An increased growth of whiskers, spikes and wires induced by the presence of metals from the metallurgical silicon was found. Nevertheless, crystalline silicon thin-film solar cells were fabricated on metallurgical substrates with efficiencies up to 7.4%.

This work proves that in-situ processes can be applied with comparatively low effort to crystalline silicon thin-film solar cells. These processes can simplify the actual fabrication sequence and may enable the use of low-cost silicon substrates. With such improvements, the crystalline silicon thin-film solar cells are brought closer to an industrial application.

8 ^Outlook

This thesis showed several applications of high-temperature CVD processes for crystalline silicon wafer and thin-film solar cells. Even though the homogeneity restrictions in terms of layer thickness and doping are not as strict for the application of solar cells as for microelectronics, further improvements are necessary to apply the processes described here more reliably and reproducibly.

The good results shown on small areas still have to be transferred to large areas.

The high potential of the n-type emitter epitaxy was already demonstrated within this thesis. However, the emitter profiles still have to be optimised for screen-print contacted cells. The substitution of the standard POCl₃ diffusion with the epitaxial emitter would lead to a further decrease in the total cost for the epitaxial wafer-equivalents. The applicability to industrial processes should then facilitate the introduction of this concept into the market.

Higher lifetimes and no light-induced degradation are imporant arguments in favour of the fabrication of n-type solar cells. However, good surface passivation layers compatible to industrial processes are still missing.

Alternative approaches are thin-film solar cells with rear junction emitters.

Figure 8-1 shows the conventional approach (A) and an epitaxial wafer-equivalent with a rear side emitter (B). The advantage here is that the front surface is easily passivated with established methods from the PV industry.

Other solar cell concepts, such as the laser fired rear access (LFA) or the thin-film emitter-wrap through (EWT) cells (Section 2.4) will benefit from the in-situ deposited emitters as well.

mg, mc or Cz p⁺ Si substrate p epitaxial base

p⁺ epitaxial BSF n⁺ emitter

porous intermediate layer texture

mg, mc or Cz p⁺ Si substrate n epitaxial base

p⁺ epitaxial emitter n⁺ FSF

porous intermediate layer texture

A B

Figure 8-1: Conventional epitaxial wafer-equivalent with front side emitter (A) and rear junction epitaxial wafer-equivalent (B).

Further in-situ processes, such as the HCl texture or the porous silicon intermediate layers, have to be investigated in more detail. For use as an internal reflector, the porous silicon must be thicker and have a higher pore density.

HCl-textured solar cells are still hindered by poor electrical properties. For a sucessful application of HCl texture the process needs to be optimised to yield a almost damage-free surface. HCl gettering of the substrate would allow to use cheaper feedstock with a higher metal impurity concentration. Here, the time of

HCl-textured solar cells are still hindered by poor electrical properties. For a sucessful application of HCl texture the process needs to be optimised to yield a almost damage-free surface. HCl gettering of the substrate would allow to use cheaper feedstock with a higher metal impurity concentration. Here, the time of

Im Dokument High-temperature CVD processes for crystalline silicon thin-film and wafer solar cells (Seite 136-186)