Graded base profile

further improved by decreasing the base doping profile towards the pn-junction, which results in a positive electrical field due to a gradient in the quasi-fermi levels caused by the dopant gradient. Due to the potential drop, the minority carriers are subjected to drift in the direction of the pn-junction, which results in an increased effective diffusion length [14,

84]. The use of graded doping profiles in solar cell bases was introduced in the 1960s by Wolf et al. [85]. At that time the realisation of such electric drift fields was difficult and only in the 1990s the first cells of silicon layers with graded profiles could be grown by LPE [86]. Nowadays it is easy to implement a graded profile during an epitaxial growth by CVD and investigations of a possible efficiency enhancement of the EpiWE due to drift fields were performed in the scope of this thesis. Figure 4-15 compares a graded profile to a constant base doping, both grown in the RTCVD100. The dip of the profile between the substrate and the base is explained elsewhere [47] and appears to be due to a non-optimised gas system.

Calculations – It is helpful to examine the analytic formula of the effective diffusion length [87-89]. The general transport equation of minority carriers can be solved with the assumptions of a constant lifetime τ and diffusion coefficient D. An effective diffusion length can then be defined by

⎟⎟

where L is the diffusion length in the absence of an electric field and EC is the critical field

Figure 4-15: Spreading resistance profiling of epitaxial layers grown in the RTCVD100 with graded (dots) and constant (squares) doping profiles.

dx

An exponential distribution of the doping N(x) = N₀ exp(αx) simplifies the calculations to

where α is the exponential slope, dbase the base thickness, N_rear the carrier concentration at the rear of the base and N_front at the pn-junction. The effective diffusion length can then be approximated to Leff = L(αL+1). For the profile shown in Figure 4-15 a value of α = 0.084 µm^-1 is calculated. Hence for diffusion lengths of 15 µm and 70 µm we obtain effective diffusion lengths of 34 µm or 480 µm, respectively. However, the extremely high enhancement of the diffusion lengths does not lead to an equivalently high increase in the cell efficiency [84] as other factors, such as the effect on the open circuit voltage V_OC and recombination mechanisms, have to be considered.

Simulations – PC1D simulations with graded doping profiles were performed by adding an exponential rear diffusion with the depth factor set to be the base thickness. Two different Nrear values were tested with a fixed Nfront of 1x10¹⁶ cm

-3. Figure 4-16 shows the cell efficiency for 0.1 and 1 µs base lifetimes and two graded profiles with Nrear = 1x10¹⁸ and 1x10¹⁷ cm^-3. For reference the constant profiles with NA = 1x10¹⁶ and 1x10¹⁷ cm^-3 are shown. The improvement from a higher constant doping concentration is clearly seen for both lifetimes, due to the large enhancement of the open circuit voltage, as discussed in the previous section. For both lifetimes an improvement in the efficiency is seen with the graded profile, even though for 1 µs base lifetime the gain is only relevant at higher base thicknesses. Obviously, the gain is larger for lower base lifetimes. A higher electrical drift field is provided by varying the dopant density by two orders of magnitude (dotted line), which results in a larger gain in efficiencies for thicker layers. This effect was also found by Weber et al. for cells with no optical confinement [84]. When an effective light trapping is present in the cell structure hardly any improvement is achieved with a drift field [84]. In conclusion, a drift field is only relevant with small minority carrier lifetimes and when no light trapping is present in the solar cell. Majumdar et al. simulated that a small negative drift field would enhance the efficiency for cells with high base lifetimes [88]. This is the case as the opposing field only barely affects the short

circuit current density, whereas the decrease of the open circuit voltage can be counteracted by the decrease of the dark saturation current density. Experiments to prove this behaviour still need to be performed.

5 6 7 8 910 20 30 40 50 60

10 11 12 13 14 15

Carrier concentration [cm^-3] 1x10¹⁶ - 1x10¹⁷ 1x10¹⁶ - 1x10¹⁸ 1x10¹⁶

1x10¹⁷ τ = 0.1µs

τ = 1µs

η [%]

Base thickness [µm]

Figure 4-16: Efficiency η dependency on the base thickness for different doping profiles and lifetimes.

Experimental realisation – Solar cells of EpiWEs on highly-doped Cz wafers were fabricated with the graded base profile shown in Figure 4-15.

Additionally, RexWE solar cells were fabricated on off-spec cast mc-Si to investigate the effect of a graded profile for lower base lifetimes. Amorphous SiC served as intermediate layer, followed by a polycrystalline BSF, the grains of which were enlarged by zone-melting [35]. The subsequent epitaxial base growth was performed either with a graded or constant doping profile. The average cell results for both wafer-equivalents are summarised in Table 4-5. The EpiWEs show only a small increase in the short circuit current density JSC of 0.8 mA/cm² for the cells with a graded profile. As shown in the simulations, the increase in JSC is not very important when the base lifetime is higher than 1 µs, which is the case for the cSiTFs grown on Cz substrates. Figure 4-17 shows the measured open circuit voltage VOC and short circuit current density JSC and the corresponding simulations. The previous simulations showed that higher increases in JSC and the efficiency are expected for cells with lower base lifetimes. The RexWE show only poor solar cell performance, but the advantage of the graded profile is beyond question. A gain of more than 1 mA/cm² was measured and a large increase in open circuit voltage V_OC of nearly 60 mV.

Furthermore, it seems that the solar cell process is more stable when applying a

Figure 4-17: Dependence of open circuit voltage VOC and short circuit current density JSC on the base thickness for the applied graded and constant doping profiles for a lifetime of 5 µs.

Experimental values are marked by symbols.

Table 4-5: Solar cells with constant and graded doping profiles for recrystallised and epitaxial wafer-equivalents.

Silicontetrachloride (STC) and trichlorosilane (TCS) are both common precursors for silicon deposition. While only TCS is routinely used for CVD in our group, epitaxial layers deposited with STC are investigated in this section in terms of the crystal quality and solar cell performance. In order to evaluate the applicability of the deposition process with STC, the gas conversion yield and the deposition profiles were examined. The quality of the layers were investigated by etch pit density measurements and solar cells.

Gas conversion yield – The gas conversion yield can be calculated based on equilibrium calculations with the program EQS4WIN from Mathtrek [90]. It is found that the gas conversion efficiency mainly depends on the Cl/H ratio rather

than on the temperature. Lower Cl/H ratios are needed for STC to reach the same gas conversion efficiency as for TCS. The theoretical limit of the gas conversion efficiency was reached by the experiment, resulting in a highest conversion yield of 69% at 1300°C and 3% Cl/H ratio.

Deposition profiles – Figure 4-18 shows the CVD rate depending on the sample position in the reactor for STC at 1300°C and varying Cl/H ratios and TCS at 1170°C. The greater thermal stability of STC requires temperatures above 1100°C in order to get sufficiently high deposition rates of 0.2 to 1 µm/min [23]. In order to get a similar deposition rate, the deposition temperature for STC needs to be more than 100°C higher compared to the deposition of TCS. The TCS process shown in

Figure 4-18 (down triangles) reached a deposition rate of 6 µm/min, in contrast to a maximum of 4.5 µm/min for the best STC process (not shown).

Furthermore, the deposition in the gas flow direction is very difficult to adjust.

Due to the high amount of chlorine in the gas and inhomogeneities in temperature, the reaction over the carrier is not in equilibrium and etching of the wafers occurs.

Etch pit densities – Epitaxial layers grown with STC or TCS on Cz substrates show similar EP densities between 10³ and 10⁵ EP/cm². However, one has to keep in mind, that the epitaxial layers deposited with STC were deposited at 100°C higher temperature than the TCS layers.

0 10 20 30 40

Figure 4-18: Deposition profiles for STC at 1300°C and TCS at 1170°C for different Cl/H ratios.

Solar cells – Solar cells were fabricated on highly-doped Cz and mc substrates (Table 4-6). Very homogeneous results are achieved for the solar cells fabricated with the STC precursor. High open circuit voltages are found for the STC solar cells, which is due to a different base doping. The solar cells fabricated with the TCS precursor have a base doping of 4x10¹⁶ cm^-3 resulting in an open circuit voltage VOC of 635 mV, whereas the STC solar cells have a base doping of 8x10¹⁶ cm^-3, which increases the open circuit voltage to a value of 650 mV (see Section 4.3.4). Due to an increased base thickness of 35 µm for the cSiTF on Cz, values above 30 mA/cm² for short circuit current density JSC are reached. The epitaxial layers on mc have thinner bases and therefore lower short circuit current densities are measured. Maximum measured cell efficiencies on Cz and mc are 16.1% and 14.5% for the STC precursor and 15.7% and 14.0%

for the TCS precursor, respectively. The slightly higher values of the STC precursor are mainly due to the different doping in the base. With either precursor very good results can be achieved.

The electronic quality of the best STC cell was additionally characterised by SR-LBIC⁶. Figure 4-19 shows that high effective diffusion lengths up to 70 µm are measured. Over the entire cell area, the diffusion length Leff is higher than the base thickness of 20 µm. Points of low lifetime are shown in the left top corner, limiting the cell performance.

Figure 4-19: Spectrally resolved light-beam induced current (SR-LBIC) map of the best crystalline silicon thin-film solar cell deposited with STC.

6 For ‘spectrally resolved light-beam induced current’ measurements, a laser beam of approximately 50 µm is scanned over a contacted solar cell and the JSC and reflection is measured simultaneously. Therefore, an effective diffusion length can be determined locally. This can be performed for different wavelengths, corresponding to the depth in the wafer.

Table 4-6: Solar cell results for TCS and STC precursors on different highly-doped substrates. Asterisks (*) mark values are confirmed by ISE CalLab.

This chapter showed the optimisations performed to improve the cell efficiency of the epitaxial wafer-equivalents. The efficiency of the crystalline silicon thin-film solar cells was increased to a value of 16.1% on Cz and 14.5% on mc substrates by optimising the most important process steps.

The substrate preparation was investigated in terms of the pre-deposition cleaning of the Cz substrate. A good correlation between etch pit densities and open circuit voltages was found within larger deviations. RCA and Plasma pre-cleanings resulted in the highest efficiencies.

The influence of impurities in the substrates was studied as they depend on the block position and on the gettering of mc silicon. In the top of a highly-doped mc ingot a higher concentration of impurities was found, decreasing the open circuit voltage and the crystalline silicon thin-film solar cell performance.

Gettering by POCl₃ diffusion improves the average open circuit voltage by 13 mV.

In order to increase the cell efficiencies, the doping profiles were optimised. It was found that an epitaxial BSF decreases the short circuit current density when the substrate lifetime is higher than 0.1 µs. Minority carriers generated in the substrate are then hindered to diffuse into the base. However, for substrates with lower lifetimes or high interface recombination rates, a BSF is essential.

A high base lifetime is the key parameter to obtain high efficiencies. From comparisons with simulation results, carrier lifetimes between 1 and 5 µs for epitaxial base layers grown in our reactors on Cz substrates have been found.

With those high base lifetimes, a large gain in the short circuit current density is

possible for thicker bases. Epitaxial layers of low lifetimes were found to have optimum base thicknesses below 20 µm. Furthermore, simulations and experimental results showed an optimum constant base doping of 8x10¹⁶ cm^-3 for solar cells with a 120 Ω/sq. POCl3 emitter. The influence of positive drift fields in the base was found to be only relevant in the case when minority carrier lifetimes are short and no light trapping is present.

5 Epitaxy of emitters

This chapter presents the application of silicon epitaxy for the emitter formation. A brief overview describes emitter deposition processes for photovoltaic applications, the advantages of epitaxial emitters and their restrictions with respect to the deposition process. Wafer solar cells with epitaxial emitters of p-type and n-type are presented. Finally the concept is applied to p-type thin-film solar cells, describing in detail the design of the emitters and their performance with evaporated and screen-printed contacts.

5.1

Introduction

5.1.1 Advantages of emitter deposition in photovoltaics

Nowadays, many different methods of emitter deposition are known and two of the most relevant techniques for solar cells are mentioned here. For instance, emitter depositions for III-V solar cells are accomplished by metal organic chemical vapour phase epitaxy (MOVPE). Doping is achieved by simply adding the corresponding dopant to the growth precursor. Usually, the doping profile is a box-section, but this can easily be varied. III-V multi-junction solar cells, for example, consist of several in-situ grown junctions [91]. A further application of emitter depositions is silicon hetero-junction solar cells, for which the amorphous silicon emitters are deposited by hot wire CVD (HWCVD) or plasma enhanced CVD (PECVD). In this case an intrinsic layer is necessary for a beneficial extended junction between the deposited n-type a-Si:H emitter and the p-type c-Si substrate. Due to the fact that an intrinsic a-Si:H has a lower defect density than a doped a-Si:H layer, a reduction of the trap-assisted tunnelling recombination rate at the a-Si/c-Si interface occurs. However, the growth of thin and highly conductive layers with these methods is challenging [92].

Chu et al. applied the epitaxial growth of an emitter by high-temperature CVD back in the 1970s [93]. They grew pn-junctions in-situ directly on metallurgical recrystallised silicon. At that time only low cell performance was achieved due to the very low quality of the substrates. For this reason no optimisation of the emitter was attempted. However, today good results are

achieved on highly-doped mc substrates (Section 4.2.3), which enables a closer look at the performance of epitaxial emitters.

The epitaxial growth of an emitter by high-temperature CVD has many advantages. Firstly, the epitaxy is a quick process of less than one minute, in contrast to the time-consuming POCl3-diffusion process that takes approximately 50 minutes for the emitter formation [94]. Particularly with a reactor such as the ConCVD, where a high throughput can be reached, emitters could be realised in consecutive chambers after the growth of the base. Cuevas et al. found that for good passivated surfaces, thick and moderately-doped emitters result in higher cell efficiencies [95, 96]. So far, this is achieved in two time-consuming diffusion steps. The epitaxial emitter can be varied in profile and therefore a moderately-doped blue-sensitive emitter can easily be realised [97]. Furthermore, no previous dopant deposition is necessary when growing by epitaxy, as the emitter is grown in-situ by adding the dopant gas to the silicon precursor. No Phosphorus silicate glass is formed, as in the case when using an oxygen-containing dopant [98]. Therefore, no chemical etching is needed after the emitter formation. Nearly all these advantages are based on a high-quality and high-throughput silicon deposition. However, there are also limitations due to the deposition process, as described in the following section.

5.1.2 Limitations of the deposition process and reactor The epitaxial layers used in this work

were grown in the lab-type reactors developed at Fraunhofer ISE. The optimisation of the emitters has proven difficult because of the relatively high inhomogeneity of layer thickness and doping concentrations described in Section 3.3.3. Figure 5-1 shows the sheet resistance mapping of a 10x10 cm² wafer with an epitaxial emitter and PH₃ flow during cooling. A large

deviation of ± 50 Ω/sq. in sheet resistance is present, which exceeds the thickness inhomogeneity of the silicon deposition (Figure 3-10). The superimposed phosphine diffusion is also very inhomogeneous, which was

10 20 30 40 50 60 70 80

Figure 5-1: Sheet resistance mapping of an epitaxial emitter with PH3 diffusion during cooling.

confirmed by the measurement of a separate diffusion. Thin emitter layers are difficult to grow because of the deposition rate of 1 µm/min of our reactors. In order to reduce the layer thickness, new process parameters would have to be defined that achieve a lower deposition rate while maintaining high epitaxial quality.

The epitaxial growth is performed at temperatures above 1000°C, so impurity diffusion to the lower contaminated substrate or epitaxial layer occurs.

Therefore, the longer the sample is kept at elevated temperature, the more the doping profiles are blurred. However, due to the low diffusivity of group III and V impurities compared to the epitaxial growth rate of silicon [50], the diffusion is locally abrupt. In order to minimise the width of the junctions and to avoid cross-doping, shallow undoped layers between the p- and n⁺-regions may be introduced [99]. The intrinsic layers are doped by diffusion during the growth and the subsequent oxidation.

Additionally, a high background doping of approximately 1x10¹⁴ cm^-3 is present in the RTCVD reactors [47]. This value depends on the reactor history and is especially noticeable after a highly-doped n-type diffusion, as shown e.g.

in Figure 5-28. To obtain a constant and low doping background, wafer dummies should be changed after each deposition and the quartz carrier should be cleaned. Of course, this is laborious and there is an alternative: a thin silicon layer can be deposited prior to the epitaxy with the samples outside of the deposition chamber. This coats the dummy wafers and the sidewalls of the reactor, hindering the dopant out-diffusion of the over-grown layer during the growth. Additionally, between the base and the emitter depositions, the reactor is purged for 10 minutes with hydrogen to eliminate remaining diborane residues and to avoid cross-doping. This should result in a more abrupt pn-junction.

As shown previously in Section 3.2.4.2, the phosphorus incorporation depends on the growth rate. The gas depletion in the RTCVD160 is quite high and the growth rate in gas flow direction on a 10x10 cm² wafer decreases from approximately 3 to 1 µm/min (see Section 3.3.3). Therefore, in a standard quasi-continuous deposition, the incorporation of phosphorus will be initially lower and increases with higher growth rates. At high temperatures, inhomogeneity in doping will be blurred by the Gaussian diffusion during the process, but it still has to be taken into account when emitters are grown at temperature below 1150°C.

5.2

p-type emitters on n-type wafers 5.2.1 Approach and solar cell process

In the last years research on n-type silicon has intensified. The major reason is that phosphorus-doped silicon has higher and more stable lifetimes than boron-doped silicon at the same purity level [100, 101]. Additionally, no light-induced degradation occurs as the boron-oxygen complex responsible does not exist

In the last years research on n-type silicon has intensified. The major reason is that phosphorus-doped silicon has higher and more stable lifetimes than boron-doped silicon at the same purity level [100, 101]. Additionally, no light-induced degradation occurs as the boron-oxygen complex responsible does not exist

Im Dokument High-temperature CVD processes for crystalline silicon thin-film and wafer solar cells (Seite 54-0)