SC/MP SERIAL INPUT/OUTPUT OPERATIONS
THE SC/I\IIP INSTRUCTION SET Table 3-4 lists the SC/MP instruction set
Memory reference instructions are shown as having either full or limited addressing capability. Full addressing capability is identified in the operand as follows:
It' OISP (X)
T '" ,,' ,
If P""'"1. X "",d, '0"" .2 0,P3, ",d ;"d",d addressing is specifiedMust always be present. Specifies a program relative displacement. '
- - - I f
present. specifies increment or auto-decrement addressing.Thus. the real options associated with full addressing capabHity are:
DISP Direct. program relative' addressing DISP(X) Direct. indexed addressing
@DISP(X)ALJto-increment or auto-decrement addressing'
limited addressing capabilities do not include the auto-increment and auto-decrement feature. The operand field for instructions with limited addressing capability is shown as follows: '
OISP (X)
r r
If pre""" X ,,,,,d,'0' •
I, .20'
P3 ",d ;"d.,""addressing is specified
Must always be present. Specifies a program . relative displacement.
The serial I/O instruction inputs serial data via the high-order bit of the Extension register. and/or outputs serial data via
. the low-order bit of the Extension register. "
The serial 110 instruction works as a on~-bit right shift of the Extension register contents. withbitO being s'hifted to the SOUT pin and the SIN pin being shifted into bit 7. This has been illustrated along with the logic description.
It is worth noting that SC/MP has no Jump-to-Subroutine instruction: rather. the XPPC instruction is used to exchange the contents of the Program Counter with the contents of a Pointer register. In very simple applications (and those are the applications for which SC/MP is intended) this is a very effective scheme. Providing subroutines are not nested. a subroutine's beginning address may be stored in a Pointer register. then execution of XPPC moves the subroutine's starting address to the Program Counter. thereby executing the subroutine ~ but at the' same time. the Program Counter contents are stored in the Pointer register. thus preserving the return address. At the conclusion of the subroutine. execution of another XPPC instruction is all tha,t is needed to return from the subroutine. The only penalty paid is that one Pointer register is out of service while the subroutine is being executed. If all Pointer registers are needed by the subroutine. or if subroutines are nested. then the return address which is stored in the Pointer register must be saved inmemory. In these more complicated applications. one of the Pointer registers will probably be used as a Stack Pointer. 'and addresses will be saved on the Stack.
This type of subroutine access. while it may appear primitive to a minicomputer programmer. is very effective in simple microcomputer applications.
The following symbols are used in Table 3-4.
AC Accumulator
C DATA DISP E
Carry status
An 8-bit binary data unit
An 8-bit signed binary displacement The Extension register
c w
~ a::
0
D-a:: 0
u ~
en
wI-<
U 0
CI) CI) <
~
w z a:: 0 CD
CI)
0
~ <
< c
@ EA
E<i>
IE O PC X SIN SOUT SR Z
@ X<y.z>
@DISP(X)
[ ]
[[ ]]
A V
¥
Effective address. determined by the instruction. Options are:
DISP EA is [PC]
+
DISP DISP(X) EA is [X]+
DISP@DISP(X) EA is [X] if DISP ~ O.
EA is [X]
+
DISP if DISP < 0;in both cases [X]-[ X]
+
DISP after EA is calculated.The ith bit of the Extension register Interrupt Enable
Overflow status Program Counter
One of the three Pointer registers Serial Input pin
Serial Output pin Status register Zero status Auto-increment flag
Bits y through z of a Pointer register. For example. P3 <7.0> represents the low-order byte of Pointer register P3.
This designates the available addressing modes for the SC/MP. as described above. In all three of the ad-dressing modes. if -128 is specified for DISP. the contents of the Extension register are used instead of DISP.
Contents of location enclosed within brackets. If a register designation is enclosed within the brackets.
then the designated register's contents are specified. If a memory address is enclosed within the brackets. then the contents of the addressed memory location are specified.
Implied memory addressing; the contents of the memory location designated by the contents of a register.
Logical AND Logical OR
Logical Exclusive-OR
Data is transferred in the direction of the arrow.
Data isexchanged between the two locations designated on either side of the arrow.
Under the heading of STATUSES in Table 3-4. an X indicates statuses which are modified in the course of the instruc-tion's execution. If there is no X. it means that the status maintains the value it had before the instruction was
ex-ecuted. .
Table 3-4. SC/MP Instruction Set Summary
STATUSES
TYPE MNEMONIC OPERAND(SI BYTES OPERATION PERFORMED
C 0
SIO 1 [E<i-l >]-[E<i>]
SOUT - [EO]
g
[E7l-SINShift the Extension register rigHt one bit. Shift bit 0 of the Extension register to the output Pin SOUTo Shift the data at input pin SIN into bit 7 of the Extension register.
u.. w
@ DISP(XI
~~Q lD 2 [AC]-[EA]
«a:- load Accumulator from addressed memory location.
~ ~"~
ST @ DISP(XI 2 [EA]-[AC]Q. W « Store Accumulator contents in addressed memory location.
~
ADD @ DISP(XI 2 X X [AC]-[AC]+ [EA]+ [C]
w Add binary to AcciJmulator the addressed memory location's contents with carry.
u z DAD @ DISP(XI 2 X [AC]-[AC] + [EA] + [C]
w a:w Add decimal to Accumulator the addressed memory iocation's contents with Carry,
~~ CAD @ DISP(XI 2 X X [AC]-[AC]+ [EA]+ [C]
~ffi
>Q. Add complement of addressed memory location's contents with Carry to AccumulatOr.
a:O AND @ DISP(XI 2 [AC]-[AC] A [EA]
0>
~a: AND Accumulator with addressed memory location's contents.
wO OR @ DISP(XI 2 [AC]-[AC]V [EA]
"> ~~ w OR Accumulator with addressed memory location's contents.
a:~
«0 XOR @ DISP(XI 2 [AC]-[AC]¥ [EA]
Oz Exclusive-OR Accumulator with addressed memory location's contents.
~« u IlD @ DISP(XI 2 [EA]-[EA]+l; [AC]-[EA]
w Increment addressed memory iocation's contents, then load into Accumulator.
en
DLD @ DISP(XI 2 [EA]-[EA]-l; [AC]-[EA]
Decrement addressed memory location's contents, then load into Accumulator,
~
0 LDI DATA 2 [AC]-DATAw :E Load immediata into Accumulator,
:!
~" ADI DATA 2 X X [AC]-[AC]+DATA+ [C]
Add binary immediete, Add Carry to result,
a: DAI DATA 2 X [AC]-[AC] + DATA + [C]
w Q. Decimal add immediate, Add Carry to result,
0
w CAl DATA 2 X X [AC]-[AC] + DATA
+
[C]'I-« Add the contents of the Accumulator to the complement of the immediate data value, Add
Car-0 w ry to result.
~ ANI DATA 2 [AC]-[AC] A DATA
~ AND immediate.
©
ADAM OSBORNE & ASSOCIATES. INCORPORATEDTable 3-4. SC/MP Instruction Set Summary (Continued)
STATUSES
TYPE MN1MONIC OPERAND'S) BYTES OPERATION PERFORMED
C 0
III
--~ ~
52
ORI DATA 2 [AC]-[AC] V DATAI!!i
OR immediate.,~g
XRI DATA 2 [AC]-[AC]¥DATA;y
Exclusive-OR immediate.;I
D. JMP
~ DISP(X) 2 [PC]-EA
::l Unco'nditional jump to effective address •
.,
JP DISP(X) 2 If [AC] ~O; [PC]-EA
w
Z Z If the Accumulator contents are greater than O. lump to effective address.
02 JZ DISP(X) 2 If [AC] =0; [PC]-EA
D.t:
:EO If the Accumulator contents equal O. jl1rnp to effective address.
::lZ
JNZ DISP(X) 2 If [AC] =0; [PC]-EA
"8
If the' Accumulator contents are not O. jump to effective address.N OJ
III LDE 1 [AC)-[E)
> Load the contents of the Extension register into the Accumulator.
0 :E XPAL X 1 [AC]-[X<7.0>]
a: Exchange the contents of the Accumulator with the low order byte of the specified Pointer
III
~ register.
(/)
C; XI>AH
III X 1 [AC)-[X<15.8>]
a: Exchange the contents of the Accumulator with the high order byte of the specified Pointer
ci: register.
III
~ XPPC X 1 [PC)-[X]
(/)
5 Exchange the contents of the Program Counter with those of the specified Pointer register.
III a: XAE 1 [AC)-[E)
Exchange the contents of the Accumulator with those of the Extension register.
W ADE 1 X X [AC)-[AC]+ [E)+ [C)
~ cs: Add binary the contents of the Accumulator and the contents 0; the Extension register. Add
Cei-a: III rry to this result.
D.
0 DAE 1 X [AC)-[AC1+ [E1+ [C)
a: III Add decimal the contents of the Extension register to those of the Accumulator. Add Carry to
~
(/) this result.
5 1 [AC)-[AC) + [E) + [C)
III CAE X X
ci: a: Add binary the contents of the Accumulator and the complement of the Extension register
con-III ~ tents. Add Carry to this result.
I/)
ANE 1 [AC)-[AC] 1\ [E)
5 III AND the contents of the Accumulator with those of the Extension register ..
a:
Table 3~4. SC/MP Instruction .Set Summary (Continued) STATUSES
TYPE MNEMONIC OPERANDiS) BYTES OPERATION PERFORMED
C 0
o
a
~I~:~~
ORE 1 [AC]-[AC]V[E](/)'(/)I~~ . OR the contents of the Accumulator with those of the Extension register.
C;'Si~
!z
XRE 1 [AC]-[AC1¥ [E)~a:IO 0
Exclusive-OR the contents of the Accumulator with those of the Extension register.
g
O-·~·V ~O~ ..
SR 1
Shift Accumulator contents right one bit. The high ~rder' bit becomes a O. The low order bit is iost.
SRl 1 ~7
..
O~w
f-Shift Accumulator contents right ~~e. bit. The Carry bit is shifted into the high order bit of the
<t
a: w Accumulator. The low order bit is lost.
110 0
Y7 oi=J
a: RR 1
..,
W f-(/)
C; Rotate Accumulator contents right one bit. Rotate the low order bit of the Accumulator into the
w high order bit.
a:
RRl ·1
4H7 .., oi=J.
Rotate Accumulator contents 'right through Carry.
f- DINT 1 [lE]':-O
110
:l Disable interrupts.
a: a:
lEN 1 [lE]-l
w
f-Enable interrupts.
~
CCl 1 0 [C]-O
: Oear Carry.
(/) SCl ' .. 1 1 [C]-l
:l f- Set Carry.
<t
1 . [AC]-[SR]
f- CSA
(/) load the contents of the Status register into the Accumulator.
CAS 1 [SR]-[AC]
load the contents of the Accumulator into the Status register.
Hf'olT 1 Pulse the H-Flag
NOP 1 No Operation.
DlY DATA 1 Delays CPU for a number of cycles equal to:
13 + 2(ACI + 2DATA + 290ATA
'.
w c
~ a:
o a.
a: o o
~ u) w ~
g
en(I)
<
o/J w Z
o a:
In (I) o
~ <
c <
@
The following symbols are used in Table 3-5:
aa Two binary digits designating the Pointer register:
00 Program Counter 01 Pointer Register 1 10 Pointer Register 2 11 Pointer Register 3
m One binary digit specifying address mode:
o
Program Relative or Indexed ,': . '. . 1 Immediate or Auto-increment or Auto-decrementPP Two hexadecimal digits representing an 8-bit. signed displacement 00 Two hexadecimal digits representing 8 bits of immediate data
Where two numbers are given - for example. 9/11. thefirst is execution time when no jump is taken: the second is
ex-ecution time when there is a jump. - ' ..
Table 3-5. SC/MP Instruction Set Object Codes and Execution !imes
INSTRUCTION OBJECT
BYTES MACHINE
CODE CYCLES
OBJECT MACHINE
. INSTRUCTION
CODE BYTES
CYCLES
ADD @DISP(X) 11110maa 2 19 JNZ DISP(X) lOoo11aa 2 9/11
PP PP
ADE 70 1 7 JP DISP(X) loooolaa 2 9/11
ADI DATA F4 PP
QQ JZ DISP(X) looo10aa 2 9/11
AND @DISP(X) llQlOmaa 2 18
pp
PP
LD ~ISP(X) llooomaa 2 18
ANE 50 1 6 PP
ANI DATA 04 2 10. LDE 40 1. 6 .
QQ LDI DATA C4 2 10 .
CAD DISP(X) lllllmaa 2 20 QQ
pp NOP 08 1 5-10.
CAE 78 1 8 OR @DISP(X) 11011maa 2 18
CAl DATA FC 2 12 PP
QQ . ORE 58 1 6
CAS 07 1 6 . ORI DATA DC 2 10
CeL 02 1 5 ." QQ
CSA 06 1 5 RR lE 1 5
DAD @DISP(X) 11101maa 2 23 RRL IF 1 ~
DAE 68 1 11 SCL 03 1 5
DAI DATA EC 2 15 SIO 19 1 5
QQ SR' lC 1 5
DINT 04 1 6 SRL 10 1 5
DLY DATA 101110aa 2 22 ST. ®OISP(X) lloolmaa 2 18
PP pp
DLY DISP 4F 2 13-131. 593" XAE 01 1 7
PP XOR @DISP(X) llloomaa 2 18
HALT 00 1 8 PP
lEN 05 1 6 XPAH X ool101aa 1 8
ILD DISP(X) 101010aa 2 22 XPAL X oollOOaa 1 8
pp XPPC X oollllaa 1 7
JMP DISP(X) l00000aa 2 11 XRE 60 1 6
pp XRI DATA E4 2 10
"Delay time depends on the value of DATA.
THE BENCHMARK PROGRAM
For SC/MP, the benchmark program looks like this:
LD T ABLE(P3) LOAD HIGH BYTE OF FIRST FREE TABLE BYTE XPAH P1 ADDRESS MOVE TO PR1 HIGH-ORDER BYTE LD TABLE+1(P3) REPEAT FOR LOW-ORDER BYTE
XPAL. P1 LDI 10HI XPAH P2
LDI 10LO
XPAL P2
LOOP LD @0(P2)