THE 3870 CONTROL CODE
THE 38~O/F8 INSTRUCTION SET
<
c <
@
In Interval Timer mode or Pulse Width mode. bits 5. 6 and 7 select the decrement time interval. The important point to note is that bits 5. 6 and 7 are cumulative. Thus. you have seven pre-scalar options shown with the control code.
In Interval Timer mode or in Pulse Width mode. the Counter register contents are decremented once every decrement time interval. A decrement time interval is equal to the internal clock pulse time multiplied by the pre-scalar. Assuming a 500 nanosecond internal clock pulse width. 010 in Control register bits 7.6 and 5 would generate a decrement time interval of 2.5 microseconds. A decrement time interval of 50 microseconds would be generated by 110 in Control register bits 7. 6 and 5.
THE 38~O/F8 INSTRUCTION SET
Table 2-1 summarizes the 3870/F8 instruction set: instructions are grouped into categories that conform with our hypothetical microcomputer Instruction set, as described in Volume I, Chapter 7. .
With reference to Table 2-1. refer to the addressing modes description for an explanation of "r". which occurs in the operand column to represent some of the scratchpad addressing options.
One of the more confusing aspects of 3870/F8 programming is understanding the ways in which data may be moved between different registers: this information is therefore summarized in Figure 2-4.
The following symbols are used in Table 2-1 : A The Accumulator
addr A 16-bit memory address C Carry status
data3 A 3-bit binary data unit data4
data5 DCO DC1 dpchr disp FMASK
H ISAR J K
o
p4 p8 . PCO
PC1
a
A 4-bit binary data unit . A 5-bit binary data unit Data Counter register Data Counter buffer
Scratchpad Data or Program Counter Half Registers. These are KU (Register 12). KL (Register 13).
au
(Register 14) and aL (Register 15).
An 8-bit signed binary address displacement
A 4-bit mask composed of a portion of the Status register (W):
3 2 0 ... Bit No.
I-~--I=FMASK
- - - Overflow status Scratchpad Data Counter Register H (Registers 10 and 11).
The Interrupt Control Bit in the Status register (W).
Indirect Scratchpad Address Register Scratchpad Register 9
Scratchpad Registers 12 and 13 Overflow status
A 4-bit I/O port number An 8-bit 1/0 port number Program Counter Stack register
Scratchpad Registers 14 and 15
S sr TMASK
Any of the following operands and Scratchpad addressing modes:
R direct address of bytes 0 through 11 . S implied addressing via ISAR
I implied addressing via ISAR. with auto-increment
of
the low-order three ISAR bitsD implied addressing via ISAR. with auto-decrement of the low-order three ISAR bits
Sign status
The register specified by the r argument
A 3-bit mask composed of a portion of the Status register (W):
2 0 ~BitNo.
TMASK
~---Sign status
~----Carry status ' - - - Zero status W The CPU Status register
Z Zero status
x<y.z> Bits y through z of the quantity x. For example. A <3.0> represents the low-order four bits of the Ac-cumulator; addr < 15.8 > represents the high-order eight bits of a 16-bit memory address
[ ] Contents of location enclosed within brackets. If a register designation is enclosed within the brackets.
then the designated register's contents are specified. If an I/O port number is enclosed within the brackets.
then the liD port contents are specified. If a memory address is enclosed within the brackets. then the con-tents of the addressed memory location are specified. .
[[ ]] Implied memory addressing; the contents of the memory location or register designated by the contents of a register
A Logical AND
V Logical OR
¥ Logical Exclusive OR
Data is transferred in the direction of the arrow
Data is exchanged between the two locations designated on either side of the arrow
Under the heading of STATUSES in Table 2-1. an X indicates statuses which are modified in the course of the instruc-tions' execution. If there is no X. it means that the status maintains the value it had before the instruction was ex-ecuted. A 0 or 1 means the status is cleared or set. respectively.
©
ADAM OSBORNE & ASSOCIATES. INCORPORATEDTable 2-1. 3870/F8 Instruction Set Summary
TYPE MNEMONIC OPERAND(S)
STATUSES-BYTES OPERATION PER-FORMED
C Z S 0
INS P4 1 0 X X 0 (A]-[P4]
Input to Accumulator from I/O port.
IN PS 2 0 X X 0 [A]-[PS]
-g
Input to Accumulator from I/O port.OUTS P4 1 [P4]-[A]
Output to I/O port from Accumulator.
OUT PS 2 [PS]-[A]
Output to I/O port from Accumulator.
LM 1 [A]-[[DCO)). [DCO]-[OCO]+ 1
Load the Accumulator via DCO and auto-increment DCO.
ST 1 [[DCOll-[Al. [OCO]-[OCO+ 11
Store the Accumulator via DCO and auto-increment OCO.
LR A.r 1 [A]-[SR]
Load the contents of the specified register. SR. into the Accumulator. Increment or decrement ISAR if specified by r.
LA A.DPCHR 1 [A]-[DPCHR]
Load Accumulator with the conterits of the specified DPCHR.
LR r.A [SR]-[A]
IU. Load the contents of the Accumulator into the specified register. Increment or decrement ISAR
U if specifl8d by r.
Z
IU LR DPCHR.A 1 [DPCHR]-[A]
a: IU Load the contents of the Accumulator into the specifl8d DPCHR.
~ IU
LR DCO.H 1 [DCO]-[H]
a:
>- Load the contents of Scratchpad registers 10 and 11 into DCO.
a: 0 LR DCO,o 1 [DCO]-[o]
:E IU Load the contents of Scratchpad registers 14 and 15 into DCO.
:E LR H,DCO 1 [H]-[DCO]
>-Load the contents of DCO into Scratchpad registers 10 and 11.
a:
i
LR o.DCO 1 [O]-[OCO]a:
. L.oad the contents of DCO lnto Scratchpad registers 14 and 15.a.
LR PC1.K 1 [PCl]-[K]
Load the contents of Register K into the Stack register.
LR K,PCl 1 [K]-[PCl]
- Load the contents of the Stack register into Register K.
LR pco,o 1 [pco]-[o]
Load the contents of Register a into the Program Counter.
PI< 1 [pCl]-[PCO], (PCO]-[oi
Save the f=:ontents of the Program cOunter in the Stack register. then ioad the contents of Register a into the Program Counter.
TYPE MNEMONIC OPERANDIS)
AS
ASD
NS
xs
OS
AM
AMD
NM
OM
XM
CM
LlSU DATA3
LlSl DATA3
DCI ADDR
US DATA4
LI DATA8
Table 2-1. 3870/F8 Instruction Set Summary (Continued)
STATUSES
BYTES ~---r---T--~~--~--~~
c z s o
x x x x
x x x x
x x o
o x x o
x x x x
x x X X
x x X X
o X X
o X X o
o X X o
x X X X
OPERATION PERFORMED
[Al-:[A]+ [SR]
Add binary the contents of the specified register to the cdntents of the Accumulator. Increment or decrement ISAR if sPecified by r.
[A]--:-[A]+ [SR]
Add decil1)al the contents of the sP<ICified register to the contents of the Accumulator; that is.
both numbers are assumed to be BCD digits. Increment Or decrement ISAR if sPecified by r.
[A]-[A] A [SR]
. AND the contents of the specified register with the contents of the Accumulator. Increment or decrement ISAR if specified by r.
tA]"":[A]¥[SR]
Exclusive-OR the contents of the specif.ect register with the contents of the Accumulator. Incre-' ment or decrement the ISAR if specified by r.
[SR]-[SR] - 1
Decrement the specified register. Increment or decrement ISAR if specified by r.
[A]-[A1+ [(DCO]]. [DCO]-[DCO] + 1
Add Accumulstor contents to the contents of the memory location addressed by OCO. Incre-ment DCO.
[A]-[A]+ [(DCO]]. [OCO]-[DCO]+ 1
Decimal add Accumulator contents to the contents of the memory location addressed by DCO.
Increment DCO.
[A]-[A] A [[DCa]]. [DCO]-[Dcol+ 1
AND Accumulator contents with the contents of the memory location addressed by DCO.
Incre-ment DCO. .
[A]-[A]V [(OCO]], [DCO]-[DCO]+ 1
OR Accumulator contents with the contents of the memory location addressed by DCO. Incre-ment DCO.
[A]-[A] ... [(DCO]i. [DCO]-[DCO]+ 1
Exclusive-OR Accumulator contents with the contents of the memory location addressed by DCO. Increment OCO.
[( DCO]] - [A1. [DCO]-[ DCO] + 1
Subtract the contents of the Accumulator from the contents of the memory location addressed . __ by OCO. !?nly the status fla.gs are affected. Increment DCO.
[ISAR <5.3 > ]-oATA3
Load immediate into the upper three bits of the ISAR.
[ISAR<2.0>]-oATA3
Load immediate into the lower three bits of the ISAR.
[DCO]-ADDR
Load immediate data into the DCO.
[A<3.0>]-DATA4
Load immediate data into the lower four bits of the Accumulator .. Clear the high four b!ts of the Accumulator.
[A]-DATA8
Load immediate data into Accumulator.
©
ADAM OSBORNE & ASSOCIATES. INCORPORATEDTable 2-1. 3870/F8 Instruction Set Summary (Continued)
STATUSES
TYPE MNEMONIC OPERAND IS) BYTES OPERATION PERFORMED
C Z S 0
AI DATAS 2 X X ~ x [A)-[A) + DATAS
1&1 Add immediate to Accumulator:
~ 4( NI DATAS 2 0 X X 0 [A)-[A) A DATAS
a: 1&1 AND i.r:nmediate with Accumulator.
a. 0 01 DATAS 2 0 X X 0 [A)-[A) VDATAS
1&1
~ OR immediate with Accumulator.
4(
Q XI DATAS 2 0 X X 0 [A)-[A).y.DATAB
1&1
Exclusive-OR immediate with Accumulator.
::E
~ CI DATAB 2 X X X X DATAB - [A]
Compare immediate: subtract Accumulator contents from immediate data. but only the status f1,!I;1.~ are affected.
PI ADDR 3 [pcll-[PCOl. [PCO)-ADDR
Save Program .Counter in Stack register. then load immediate address into Program Cou·nter.
a. BR DISP 2 [pcO)-[PCO)+DISP
::E
:;) Add immediate displacement to contents of Program Counter.
..,
JMP AD DR 3 [PCO)-ADDR. [A)-ADDR<15.B>Load irnmediate address into Program Counter.1.oad the high order byte of the address into the Accumulator,
BT . DATA3.DISP 2 If DATA3 VTMASK4 0 then [PCO)-[PCO) + DISP
OR the 3 bits of immediate data with the current TMASK.lf any resulting bit is a 1. add the dis-placement· to PCO.
BF DATA4.DISP 2 If DATA4 =FMASK. then [PCO)-[PCO)+DISP
If the 4 bits of immediate data are equal to FMASK. add the displacement to PCO.
BP DISP 2 If[S] = 1 then [PCO)-[PCO)+ DISP
Branch relative if the Sign bit is set.
Z Be DISP 2 If [e) = 1 then [PCO)-[PCO)+ DISP
0 Branch relative if the Carry bit is set.
·E BZ DISP 2 If [Z) =; 1 then [PCO)-[PCO)+ DISP
Q
Z Branc~ !.ellltive !!'!!J~ Zero bit is set.
U 0 8M DISP 2 If [S) =utnen lrCO]-[PCO)+ DISP
Z
0 .Branch relative if the Sign bit is reset.
:z:. BNC DISP 2 If [C) =0 then [PCO)-[PCO)+ DISP
Z U Branch relative if the Carry bit is reset.
4( a: BNZ DISP 2 If [Z] =0 then [PCO)-[PCO]+DISP
ID Branch relative if the Zero bit is reset.
BNO DISP 2 If (0) =0 then· [PCO]-[PCO)+ DISP
Branch relative if the Overflow bit is reset.
BR7 DISP 2 If [ISAR <2.0 » = 7 then [PCO)-[ PCO) + DISP
If the low three bits of the ISAR are not all 1s. branch relative.
Table 2-1. 3870/F8 Instruction Set Summary (Continued)
STATUSES
TYPE MNEMONIC OPERAND(S) BYTES OPERATION PERFORMED
C Z S 0
a: XDC 1 [DCO]-[DCll
'"
I- Exchange:the contents of DCO with the contents of DC1.
(/)
S LR A.IS 1 [A]-[ISAR]
"''''
~~ Load the contents of ISAR into the Accumulator.~~
LR IS. A 1 [ISAR]-[A](/) Load the contents of the Accumulator into the ISAR.
S pop
'"
1 [PCO]-[PClla: Load the contents of the Stack register, into the Program Counter.
a:
a:'"
ADC 1 0 X 1 0 [DCO]-[DCO]+ [A]"''''
I-1-1-c( Add the contents of DCO to the contents of the Accumulator, which is treated as a signed binary
(/)(/) a:
SS'" number. Store the ,result in DCO.
" , , , , I L a: a: 0
i
SR' 1 1 0 X 1 0 0--+f7
of.
Shift the contents of the Accumulator right one bit. The most significant bit becomes a O.
17
l I i
0'SR 4 1 0 X 1 0 0000
T
Shift the contents of the Accumulator right four bits. The most significant four bits become Os.
'"
SL 1 1 0 X X 0 +--17 Ot.-OI- Shift the contents of the Accumulator left one bit. The least significant bit becomes a O.
c( a:
'" ,
~
IL
0
P I
0' 0000a: SL 4 1 0 X X 0
'" T
l-(/)
S Shift the contents of the Accumulator left four bits. The least significant four bits become Os.
w a:
[A]-[M
COM 1 0 X X 0
Complement Accumulator contents.
LNK 1 X X X X [A]-[A]+C
Add the Carry to the contents of the 'Accumulator.
INC 1 X X X X [A]-[A]+1
Increment the contents of the Accumulator.
CLR 1 [Al-O
Clear the Accumulator.
©
ADAM OSBORNE & ASSOCIATES. INCORPORATEDTable 2-1. 3870/F8 Instruction Set Summary (Continued)
STATUSES
TYPE MNEMONIC OPERAND(S) BYTES OPERATION PERFORMED
C Z S O.
I- [1]-0'
CL DI 1
:I a: Set the interrupt enable- bit in the Status register •. W, to O.
a: 1&1 EI 1 (1)-1
I-!: Set the interrupt enable bit in the Status register, W.to·1.
CI.I LR W,J 1 [W]-[J)
:I I- Move the contents of Scratchpad register 9 into the Status register. W.
c(
I- LR J,W 1 [J]-[W]
CI.I
Move the contents.of the Status register, W. into Sclatchpad register 9.
NOP 1 No operation is performed. This is not a Haft.