The SC/MP memory reference instructions use program-relative direct addressing, indexed addressing, and auto-indexed addressing. All memory refererice instructions are two-byte instructions and have the following object code format:
7 6 5 4 3 2 1 0 ~ Bit No.
' - - - 00
=
PC 01 =Pl 10 =P2 11 =P37
- - - 0
=
PC-relative or indexed 1 = Auto-indexed ' - - - . ; . - - - - Opcodeo
displacement
Program relative and indexed addressing are as described in Volume I, Chapter 6. We will just re-emphasize here that all addressing in SC/MP is paged and uses the wrap-around technique - that is. there is no carry from the low order 12 bits of an address into the most significant 4 bits of an address, We mentioned this earlier when we discussed the Program Counter. and it also applies to indexed addressing. Thus. if the sum of the Index register {that is.
one of the Pointer registers) and the second object code byte contents (displacement) is more than FFF16. the Carry bit will be discarded, This may be illustrated as follows:
, Pointer register (Index register) displacement
tF B4
I
~---",<",
T ..
+---Effective Address
~
= 1 FB4 + 4D 1 F B 4 + 4 DExpected result =
2)
0 0 1 ' , ' , Discard carry.-/ \":Actual Result is 1001. Ie
Remember, all arithmetic operations during address formation, regardless of the addressing mode, obey this wrap-around technique: there is never a carry from bit 11 into bit 12.
The auto-indexing mode of addressing provided by SC/MP instructions is actually an auto-increment/auto-decrement operation. When auto-indexing is specified. the displacement. as a signed binary number. is added to the contents of a Pointer register in order to compute an effective address. If the displacement is less than zero. the Pointer register is decremented by the displacement before the memory access. If the displacement is equal to or greater than zero. then the contents of the Pointer register is the effective address and the Pointer register contents are incremented by the displacement after the memory access. This method of auto-increment and auto-decrement addressing is the same as that described in Volume I with one significant difference: SC/MP allows an address to be incre-mented or decreincre-mented by any value in the range 0 - 127 instead of just by a value of one.
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SC/MP STATUS REGISTER
sC/MP has a programmable 8-bit Status register which may be illustrated as follows:
Circled numbers represent device pin numbers to which bits of the Status register are connected,
The Carry (ey), Link (L) and Overflow (OV) status bits are typical microcomputer status bits as were desc:ribed in Volume I, Chapter 7.
,The two sense bits, sB and SA, are tied to sC/MP device pins. These two bits directly reflect the state of the logic signals applied to the device pins and thus can be used to detect external events. Although there are no SC/MP instructions that allow you to directly jump or branch on the condition of one of these bits, a sequence of mask-ing and testmask-ing instructions can be used to accomplish the same effect albeit more slowly, The SA and sB bits are read-only bits. Instructions may read the status of these two bits, but only incoming signals may ~hange t~eir
condition. For example, an instruction that moves the contents of the Accumulator to the Status register may modify any of the o~her status pits, but bits 4 and 5 will not change, The SA bit serves a dual function. If the Interrupt Epa-ble (IE) bit is set to one, the SA input serves as the interrupt input. We will di"scuss interrupt processing later in this
chapter, ' ,
FO, F1 flnd F2 are control flags that are tied to SC/MP device pins. The state of these three flags may be changed under program control and may be used to control external devices. When the state of any of these flags' is chang~d, it is immediately reflected by a change in the signal level af the associated device pin,
SC/MP. CPU SIGNALS AND PIN ASSIGNMENTS
Figure 3-2 illustrates the SC/MP pins and signals. A description of these signals is useful as a guide to the way in which an SC/MP microcomputer system works.
The 12 address lines ADOO - AD11 output memory and I/O device addresses. These are tristate lines, and may be floated, giving external logic control of the Address Bus. The four most significant address bits (A~12 - AD15) are time multiplexed on the data lines.
The eight Data Bus lines DBO - DB7 are multiplexed, bidirectional data lines through which 8-bit data units are input a'nd output, and on which statuses and address bits are output at the beginning of any input/output 6ycle.
Statuses on Data Bus lines DB4 - DB7 identify the type or purpose of the input/output cycle. The address bits on Data Bus lines DBO - DB3 are the four most Significant address bits (AD12 - AD15) which must be 'Used to generate page select signals for memory or peripheral devices. Table 3-1 ;descri~es the status and addr~ss infor-mation that is output on the Data 'Bus. Like the address'lines, the data lines are tristate. ' .f ~
'. , ' I . . , . . . .
SENS~A~ ~ENSEB, FLAGO, 1, al'lc;i 2 are pin connections for the simil~uly named Status register bits described
earlier. '. . . , '
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SIN and SOUT are used il1 ~ombination with the SIO instruction for serial input of Data to the Extension register and serial output of data from the Extension register.
The remaining Signals (excluding clock, power and ground) may be divided into bus access, Data Bus definition, and timing <::ontrol signals.
You will notice that some of the SC/Mr pins in Figure 3-2 have two sets of signal SIGNAL names: the names enclosed in parentheses reflect the nomenclature used with SC/MP- DIFFERENCES II; Aside from the ciock and power' signals which we shall discuss separately, the only BETWEEN SC/MP difference between SC/MP and SC/MP-II is in the polarity of bus access signals: Bup Request (P-CHANNEL) (BREQ/NBREQ), Enable In (ENIN/NENIN), and Enable Out (ENOUT/NENOUT), The "N;' prefix to AND SC/MP-II each of the SC/MP-II signals indicates that these signals are negative-true - as opposed to (N-CHANNEL) the positive- (or logic "1 ") true signals for the P-channel SC/MP. In the descriptions that . follow, we will use P-channel SC/MP nomenclature. If you are using the N-cnannel SC/MP-II version, you m'ust simply invert these signals.
NWDS
Xl,X2 Crystal/Capacitor Connections
-000 - DB7 Data Bus
-ADOO- ADll Address Unes
-SENSEA,SENSEB External Status Input:
-FLAGO,l,2 Flags.
-NRST Reset
-CONT Halt/Continue
-BREO (NBREO) Bus Request/Busy -ENIN (NENIN) Data Bus Enable
VGG,VSS(VCC,GND) Power and Ground -These signals connect to the System Bus. System· Busses .. This approach reflects the design philosophy behind SClMP.lt is a relatively low-cost. low-performance CPU and the designers anticipated that it would frequently be used in multiprocessor systems orin systems utilizing Direct Memory Access. Accordingly, three signals are proyided to control access to the System Busses.
SC/MP BUS ACCESS CONTROL SIGN'ALS BREQ is· used as a bus busy input indicating that some other device is using the System Busses; as an output, BREQ.is a bus request which is output when the System" Busses are free and SC/MP requires access·to the
busses. . . .
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denied access to the System Bus'ses and the' SC/MP address and data lines are held in tristate mode.I . " '.' ';""~
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ENOUT is the CPU's output response to ENIN. When output high. ENOUT indicates that ENIN is high; therefore. the CPU can gain access to the System Busses. but it has not done so. If ENOUT is low. it indicates either that ENIN is low.
therefore the CPU is being denied access to the System Busses or. if ENIN is high. then it indicates that the CPU is using
the System Busses. .
When the CPU has gained access to the System Busses, three signals identify the way in SC/MP DATA
which the CPU is using the Da~~ Bus. BUS DEFINITION
SIGNALS NADS is output to indicate that a valid address has been output on the address lines and
that the low-order four ~its of the Data Bus contain the high-order four· bits of a 16-bit
address. NADS also indicates.tti~t status information is being output on the high-order four bits of t~e Data Bus.
!'IRDS, when output by the CPU, indicates that the CPU wishes to receive data on the Data Bus.
NWDS, when output by the CPU, indicates that data is being output by the CPU on the Data Bus. NWDS may be used by external logic as a write strobe.
There are three signals which control CPU timing. SC/MP TIMING
CONTROL NRST is a system reset signal. When input low. it aborts any in-process operations. When
returned high. all programmable registers are cleared. and program execution begins with the SIGNALS instruction fetched from memory I?cation 000116.
CONT may be input to stop the CPU between instructions. When CaNT is input low. all CPU operations are halted after the current instruction execution has been completed. The CPU remains halted until CaNT goes high.
NHOLD is an input signal used during input/output operations to lengthen the allowed time interval for devices
to respond to CPU access requests. ;' .