INDEX PAGE
M (Cant.) MC6844 Data Chaining 9-119
c MC6844 Data Chaining Control Register 9-117
w MC6844 DMAC Address 8us 9-109
I-~ MC6844 DMAC Data 8us 9-109
a:: 0 MC6844 DMAC Device Select 9-109
a. MC6844 DMAC. DGRNT. TxST8. TxAKA andTxAK8 Signals 9-114
a::
0 MC6844 DMAC DROH Signal 9-114
u !: MC6844 DMAC Four-Channel Mode 9-118
en w MC6844 DMAC IRO/DEND Signal 9-113
I-~ MC6844 DMAC Two-Channel Mode 9-117
C3 MC6844 DMAC TxAKA and TxAKB Signals 9-113
0 MC6844 DMAC. TxRON. DORT. and DGRNT Signals 9-112
en en MC6844 DMAC TxRO-TxR3 Signals 9-114
~
clJ MC6844 DMAC TxSTB Signal 9-113.115
w MC6844 DMAC <1>2 DMA Clock 9-112
z a:: MC6844 Enable/Priority Control Register 9-116
0 m MC6844 Fixed DMAPriority Arbitration 9-116
en MC6844 Interrupt Control Register 9-121
0
~ MC6844 Rotating Data Priority Arbitration 9-117
~ MC6846 Composite Status Register 9-129
c ~ MC6850 Control Register 9-59
@ MC6850 Interrupt Logic 9-59 .
MC6850 MODEM Control Signals 9-58
MC6850 Serial I/O Control Logic 9-59
MC6850 Serial I/O Data and Control Signals· 9-58
MC6850 System Reset 9-59
MC6852 Interrupt Logic 9-70
MC6852 Reset Operation 9-70
MC6852 Serialization Sequence 9-63
MC6852 Triple Data Buffers 9-65
Microcomputer Development Systems. Simple 25-4
Microcomputer Development Systems. Simulating 25-4
MicroNova I/O Bus 19-12
MicroNova Memory Bus 19-12
MODEM Control Signals 9-58
Monitor: 25-5
Motorola A and B Series Parts 9-2
Multiple Device Selects and Bus Loading (8085A) 5-11
Multi-8086 Clock Signals. Synchronizing 20-79
N NEC 8080A External Interrupt Differences 4-24
NEC 8080A Hold Differences 4-17
NEC 8080Alnstruction Execution Time Differences 4~33
NEC 8080A Instruction Set Differences 4-24.
NEC 8080A Interrupt Acknowledge Differences 4-24
NHAL T and CONTIN Signals are Multifunctional 15-15
Nova Direct Memory Addressing 19-6
Nova Indirect Indexed Addressing 19-8
Nova Indirect Page Zero Addressing 19-6
Nova Indirect Program Relative Addressing 19-7
Nova I/O Device Address Space 19-22
Nova I/O Device Addressing 19-9
Nova I/O Device Busy and Done $tatus 19-20
Nova I/O Device Registers 19-21
Nova Multiple Indirect Addressing· • 19-9
0 Object Programs. Relocatable 25-7·
Overflow and Carry Status in Chip Slice Logic 22-5 ..
INDEX P
R
s
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.QUICK INDEX (Continued)
PACE Address Latches and Decoders '
PACE and INS8900. Cycle-Stealing DMA during Internal Machine Cycles PACE and INS8900 Data Input Cycle
PACE and INS8900 Data Output Cycle PACE and INS8900 Direct Addressing Options P~CE a'ld INS8900 Direct Indexed Addressing PACE and INS8900 Execution Speed
PACE and INS8900. Extend Used to Suspend I/O During DMA Operations PACE and INS8900. Floating System Busses
pACE and INS89dO Halt State .
PACE and INS8900 Internjpt Acknowledge and Return from Interrupt PACE and INS8900 Interrupt Pointers
PACE and INS8900 Interrupt Priorities PACE and INS8900 Interrupt Response
PACE and INS8900lnterrupts. Enabling and Disabling PACE and INS8900 Logic Level
PACE and INS8900 Machine Cycle PACE and INS8900 Machine Cycle Types
PACE and INS8900 Non-Maskable (Level 0) Interrupt PACE and INS8900 Power Supply
PACE and INS8900 Processor Stall PACE and INS8900 Signal Differences PACE and INS8900 Signal for Slow Operations PACE and INS8900 Split Base Page
PACE and INS8900 Split Base Page to Address I/O . PACE and INS8900 Stack Interrupts
PACE and INS8900 Systems Cycle-Stealing DMA
PACE and INS8900 Systems DMA Block Data Transfers Initiated by External Logic PACE Clock Signals .
PACE CPU and INS8900 Registers during Interrupts. Saving PACE DP8302 STE Clock Frequency
PACE Level 0 Interrupt Problems PACE Level 0 Interrupt. Return from PACE MILE Used in an SC/MP System. The PACE Stack Interrupt Problems
Preventing Simultaneous Selection of I/O and Memory on an 8085A Preventing Transient Selection on an 8085A
Processor Stall and Level 0 Interrupt Similiarities Program Linking
PSU Address Space
Read-Only Memory. IM6100 Subroutines in Relocatable Loader
Relocatable Object Programs Relocating Assembler Reset. 8048. 8748. and 8035 Return from PACE Level 0 Interrupt ROMC State
Saving INS8900 and PACE CPU Registers During Interrupts SC/MP and SC/MP-II
SC/MP and SC/MP-II. Signal Differences Between SC/MP Bus Access Control Signals
SC/MP Bus-Sharing Control Signals SC/MP Busses. Buffering
SC/MP Control Techniques in Multiprocessor Applications SC/MP Data Bus Definition Signals
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QUICK INDEX (Continued)
SC/MP Data Bus, Demultiplexing the SC/MP Data Input Cycle
SC/MP Data Output Cycle
SC/MP DMA and Multiprocessor Logic
SC/MP ENOUT Signal Used to Establish Access Priorities·
SC/MP Instruction Execution Speed SC/MP 110 Cycle Status Information SC/MP 110 Cycle, Suspension of an
SC/MP 110 with Bus Access Logic Continuously Enabled SC/MP Logic Level
SC/MP Memory Pages
SC/MP in Multiprocessor Systems
SC/MP NHOLD Signal for Slow 1/0 Operations
SC/MP (P-Channell and SC/MP-II (N-Channell, Signal Differences Between SC/MP Return-from-Interrupt Technique
SC/MP Serial 110
SC/MP System, The PACE MILE Used in an
SC/MP System, The 8212 Used as an Output Port in an SC/MP Systems, The 8212 I/O Port Used in
SC/MP Timing Control Signals
SC/MP-II (N-Channell and SC/MP (P-Channel), Signal Differences Between Select Problem with 8085
Service, After Sales
Sign Status in Chip Slice Logic
Simple Microcomputer Development Systems Simulating Microcomputer Development Systems
Standard Memory Devices Connected to an 8048 Series Microcomputer Subroutine Library
Suspension of an SC/MP 110 Cycle Synchronizing Multi-8086 Clock Signals System Timing Element
TMS 1000 Subroutines TMS 5501 Nonstandard Features TMS 5501 Output Signal Inversion TMS 5501 Reset
TMS 5501 Wait State
TMS 9900 Backward Context Switch TMS 9900 Context Switch
TMS 9900 Direct Addressing TMS 9900 Forward Context Switch TMS 9900 Implied Addressing TMS 9900 Indexed Addressing
TMS 9900 Instruction Execution Sequences TMS 9900 Internal Operations Machine Cycle TMS 9900 Interrupt Vector Map
TMS 9900 Memory Addresses
TMS 9900 Multiple Interrupt Hardware Considerations TMS 9900 Nested Interrupt Priorities
TMS 9900 Program Memory Addressing TMS 9940 CRU Bit Utilization
TMS 9940 CRU I/O Expansion Mode TMS 9940 HOLD Logic
TMS 9940 IDLE Logic
TMS 9940 Multiprocessor System Interface -TMS 9940 Simple CRU 1/0 Mode
TMS 9940 Sync Mode
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INDEX
z-QUICK INDEX (Continued)
TMS 9980 Series Clock Logic
Transient Selection. Preventing on an 8085A TTL Level PACE Bus
Two 8255 Devices Used for 16-Bit I/O Ports with INS8900 TxAKA and TxAKB Signals. MC6844 DMAC
TxAKA. TxAKB. DMAC. DGRNT. and TxSTB Signals. MC6844 TxAKB and TxAKA Signals. MC6844 DMAC
TxRON. DQRT and DGRNT Signals. MC6844 DMAC TxRO-TxR3 Signals. MC6844 DMAC
TxR1 Signal. MC6844 DMAC TxR2 Signal. MC6844 DMAC TxR3 Signal. MC6844 DMAC TxSTB Signal. MC6844 D TxSTB Signal. MC6844 DMAC
TxSTB. TxAKA. TxAKB. DMAC. and DGRNT Signals. MC6844 Utilities
Variable Cost Contributing Factors Variable Costs
Wait States during 8085 Interrupt Acknowledge Zero Status in Chip Slice Logic
Z80 Bus Control Signals Z80 CPU Control Signals Z80 Indexed Addressing Z80 LSI Technology Z80 System Control Signals
Z80 Wait States During Interrupt Acknowledge 1650 Accumulator
1650 Counter/Timer Logic 1650 I/O Pin Logic 1650 I/O Port Registers 1650 Program Counter 1650 Program Memory 1650 Stack17-6 1650 Status Register 1650 Timing
1650 VXX Power Supply 2650A Accumulator
2650A Branch Instruction Addressing 2650A Bus Access Control Signals 2650A Bus Contents Identification Signals 2650A CPU Execution Control Signals 2650A Extended Addressing Options 2650A External Device Control Signals 2650A Index Registers
2650A Interrupt Control Signals 2650A Memory Page Selection 2650A Memory Pages 2650A Program Counter
2650A Program Relative Addressing Options 2650A Stack
2901 ALU Operations Specification 2901 ALU Source Specification
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QUICK INDEX (Continued)
3870 Clock Logic
3870 Direct Scratchpad Addressing 3870 Event Counter Mode 3870 Expansion
3870 Implied Scratchpad Addressing 3870 Interrupt Disable
3870 Interval Timer Mode 3870 Memory Addressing
3870 Pulse Width Measurement Mode 3870 r Scratchpad Addressing 3870 Reset
3870 Scratchpad Memory Addressing 3870/F8 Accumulator
3870/F8 Data Counters 3870/F8 Program Counter 3870/F8 Scratchpad 3870/F8 Stack Register
6800 Support Devices Not Compatible with INS8900 8T32 IV Byte Access Logic
8T32 IV Byte Addressing 8T32 IV Bytes
8T33 IV Byte Access Logic 8T33 IV Byte Addressing 8T33 IV Bytes
8T35 IV Byte Access Logic 8T35 IV Byte Addressing 8T35 IV Bytes
8T36 IV Byte Access Logic 8T36 IV Byte Addressing 8T36 IV Bytes
8X300 Data and I/O Addressing 8X300 Program Memory Addressing . 8X300 Rotate and Mask Logic
8X300 Shift and Merge Logic 8035.8048. and 8748 Reset 8041 Buffer Status Register 8048 and 8748 Debug Mode
8048 Series External Memory Access Mode 8048 Series Internal Execution Mode 8048 Series 1/0 Port Pin Logic 8048 Series I/O Ports
8048 Series Machine Cycles and Clock Periods 8048 Series Memory Spaces
8048 Series Microcomputer. Standard Memory Devices Connected to an 8048 Series Microcomputer. 8355 or 8755 Connected to an
8048 Series Program Memory Addressing 8048 Series Single Stepping
8048 Series Verify Mode 8048 Wait State
8048.8748. and 8035 Reset 8049 Series Microcomputers
8080A and INS8900 System Busses Compared 8080A and 8086 Registers' Compatibility 8080A Carry Status Borrow Logic 8080A Carry Status Nomenclature
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INDEX