SOSOA Clock Periods
SOSOA Data Bus Definition Signals SOSOA Direct Addressing SOSOA Implied Addressing SOSOA Instruction Status SOSOA Interrupt Control Signals
S080A Interrupt Response Using CALL Instruction SOSOA Machine Cycles
S080A Slow Memories SOSOA Timing Control Signals SOSOA Wait State Request Logic
SOS5 and SOS5A. Interrupt Differences in S085 Interrupt Acknowledge
SOS5 Interrupt Acknowledge. Wait States During' SOS5 I/O Write Timing
SOS5 Memory Read Timing S085 Memory Write Timing SOS5 Multibyte Acknowledge SOS5. Select Problem with SOS5A and SOS5
SOS5A and SOS5. Halt State in
S085A and SOS5. Interrupt Differences in SOS5A Bus Control Signals
SOS5A Bus Idle Machine Cycle SOS5A Clock Periods
SOS5A Control Signals
SOS5A Data Bus Definition Signals SOS5A Device Select Logic SOS5A Hold Within a Halt State SOS5A Interrupt Acknowledge SOS5A Interrupt Signals SOS5A Machine Cycles SOS5A Multibyte Acknowledge
SOS5A Multiple Device Selects and Bus Loading
SOS5A. Preventing Simultaneous Selection of I/O and Memory onan SOS5A. Preventing Transient Selection on an
SOS5A Reset Signals SOS5A RIM after TRAP SOS5A Serial I/O
SOS5A TRAP Interrupt
SOS6 and SOSOA Registers' Compatibility SOS6 AX Register
SOS6 Base Relative Indexed Addressing SOS6 BCD Addition
SOS6 BCD Division SOS6 BCD Multiplication SOS6 BCD Subtraction SOS6 Bus Interface Unit (BIU) S086 BX Register
SOS6 Code Segment Register and Program Counter SOS6 Complex Control Signals
SOS6 CX Register
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QUICK INDEX (Continued)
8086 Data Memory Base Relative Addressing 8086 Data Segment and Stack Segment Registers 8086 Direct Indexed Addressing
8086 Direct Memory Addressing 8086 OX Register
8086 Execution Unit (EU) 8086 External Memory Addressing
8086 Extra Segment. Source Index and Destination Index Registers 80~6 HOLD in Maximum Mode System
8086 HOLD in Minimum Mode System 8086 Implied Memory Addressing 80~6 Indirect Addressing 808p Instruction Queue 8086 Interrupt Return
8Q~6 Interrupt Vector Table 80861/0 Port Addressing 8086 Maskable Interrupt 8086 Non-Maskable Interrupt 8086 Program Relative Addressing 8086 Reset
8086 Segment Registers 8086 Simple Control Sgnals
8086 Single Instruction Time Identified 8086 Software Interrupts
8086 Stack Segment and Stack Pointer Registers 8155 Device Reset
8155/8156 I/O Mode 0 8155/8156 I/O Mode 1 8155/8156 I/O Port Addresses 8155/8156 Timer Mode 0 8156/815p I/O Mode 0 8156/8155 VO Mode 1 8156/81551/0 Port Addresses
8212 I/O Port Used in SC/MP Systems. The
8212 Used as a Simple Input Port in an INS8900 System. The 8212 Used as an Output Port in an INS8900 System. The 8212 Used as an Output Port in an SC/MP System. The
8212 Used in an INS8900 System for Input with Handshaking. The 8224 Clock Signals
8243 Reset
8251 USART and 8253 Programmable CounterlTimer Used in INS8900 Systems. The 8253 Programmable CounterlTimer and 8251 USART Used in INS8900 Systems 8255 Devices Used for 16-Bit I/O Ports with INS8900
8255 PPI Devices Used in an INS8900 System 8259 PICU Interrupt Mask
8259 PICU Interrupt Masking
8259 PICU Interrupt Service Routine Priorities 8259 PICU Polling
8259 PICU Rotating InterruptPriorities 8284 Wait State Logic
8288 Advanced Write Control Signals 8288 Bus Controller Interrupt Signals 8288 Bus Controller Memory Protect 8288 I/O Bus Mode
8355 or 8755 .cQnnected to an 8048 Series Microcomputer 8748 and 8048 Debug Mode
8748 Programming Mode
INDEX
QUICK INDEX (Continued)
8748.8048. and 8035 Reset 8755 and 8755A
8755 or 8355 Connected to an 8048 Series Microcomputer 8755A and 8755
9080A AMD Status Difference 9440 Instruction Fetch 9440 Memory Read 9440 System Bus
PAGE 6-17 5-51 6-22 5-51 4-6 19-23 19-23 19-14
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©
INTRODUCTION
This is the first of two volumes that replace An Introduction to Microcomputers: Volume 2 - Some Real Pro-ducts. This volume describes microprocessors and dedicated support devices. Volume :3 de~cribes general sup-port devices.
We define a "dedicated" support device as one best used with its parent microprocessor. We define a
"general" support device as one which can be used w~th any microprocessor.
Unfortunately, categorizing support devices as "dedicated" or "general" is not always straightforward. Cer-tainiy IM6100 and TMS9900 support devices have' CPU interfaces which ara peculiar to the parent microprocessor, so using them with other microprocessors makes little sense. Most MC6800 microprocessor support devices are also considered dedicated because they use the MC6800 clock signal. This clock signal is automatically generated by an MC6800 microprocessor or its clock device. It can be derived quite inexpen-sively in other microcomputer systems; nevertheless, we include MC6800 support devices in Volume 2, because in our opinion the added clock logic is not compensated for by any performance capabilities over and above those which you would find in a competing device that did not require the added clock logic.
When reading Volumes 2 and 3, therefore, you should bear in mind that we have had to be subjective when deciding whether some parts should be described in Volume 2 or Volume 3. Dp not automatically use support parts described in Volume 2 without checking equivalent parts described in Volume 3. Conversely, there may be instances where your application is better served by a support device described in Volume 2. In general, you can look upon Volume 3 support devices as CPU-independent, while Volume 2 devices are CPU-dependent.
In order to cope with the rapid evolution of new parts, Volumes 2 and 3 have been printed loose-leaf. Each volumo will have six updates per year, appearing at bimonthly intervals. For Volume 2, updates will appear in November, January, March, May, July and September. Each Septembor the entire book will be reprinted, in-cluding the past year's updates. If you have inserted your updates, you will not need to buy a new book next year. For your convenience, an order form may be found at the back of this book.