In the following, process flows developed during this work are described. Structuring of metal can be done either by dry or wet chemical etch or bychemical mechanical polishing (CMP). For both methods a process flow has been established in order to make best use of existing process experience with different materials. Beside gate electrodes also substrate electrodes were considered as they are found for example in DRAM capacitors.
3.2.1 Planar Capacitors with Metallic Substrate Electrodes
DRAM memory chips require capacitors with a capacity of 25 fF and a maximum leakage current of 1 fA per cell, whereas the available area is reduced from generation to generation.
Beside surface enhancement techniques like hemispherical silicon grains(HSG) and new dielectrics metal electrodes are well suited to reach this aim.
Si
NO VG
Metal Poly-Si
Fig. 3.2: Test structure for investigation of metal substrate electrodes. The gate electrode can by struc-tured by a classical dry etch.
In order to modify the existing system as little as possible, at first only the bottom electrode and subsequently only the gate electrode are processed in metal. The former
3.2. PROCESS FLOW OF MIS-STRUCTURES 29
is done by depositing a stack of metal, dielectric and polysilicon on blanket wafers and structuring the polysilicon with a standard dry etch process to form large area capacitors as shown in Fig. 3.2. No special masks are necessary since the standard gate conductor (GC) layer can be used for this purpose.
3.2.2 Planar Capacitors with Metal Gate Electrodes
This section presents processes wherein the top electrode is structured by CMP or by non-critical dry etch processes. A development of a usual dry etch process is only worth doing, if the material system has proven its functionality. Fig. 3.3 shows two variations facilitating a relatively simple fabrication of the test structures. In both cases a thick oxide is deposited in which large area holes are etched using a special mask (Fig. 3.3a). This mask is not part of the standard CMOS-process, but should be alignable to the AA-mask for sake of simple integration into the whole process. During this work the XP-mask was dedicated to this purpose and hence the thick oxide is referred to as XP-oxide in the fol-lowing. The XP-mask is usually used for LDD implants of the PFETs but for our process these implants can also be performed via the source/drain layers.
a
Oxide Resist
b
Oxide Metal
c1
Oxide
c2
Fig. 3.3: Schematic process flow for the fabrication of metal gate electrodes. Openings which define the capacitor area are etched into a thick oxide (a). Subsequently, dielectric and gate electrode are deposited (b) and structured by either CMP (c1) or by dry etch (c2).
Etching of the XP-oxide is followed by deposition of dielectric and metal (Fig. 3.3b).
Now there are two ways to structure the electrode. Firstly, the metal on the XP-oxide can be removed by a CMP-step as shown in Fig. 3.3c1. Support structures in the large area opening help to prevent over-polishing in these areas. Secondly, metal can be structured by a dry etch process as presented in Fig. 3.3c2. For this purpose, the GC-layer is appropriate which should be drawn somewhat larger than the openings in the XP-oxide.
The etch process of the metal has to be neither selective nor anisotropic.
3.2.3 Modified CMOS Process with Metal Gate
The modified CMOS process is identical to the standard process up to gate oxidation.
Then, deposition of the XP-oxide is followed by source/drain implants as shown in Fig.
3.4a. As described in the last section, holes are etched into the XP-oxide and gate dielectric as well as gate electrode deposited and structured (Fig. 3.4b). The titanium silicide (TiSi)-formation is omitted in the modified process, while the remaining metallization is analogue
to the standard process. Passivation (TV) protects the chip from erosion. A cross section of the final structure can be seen in Fig. 3.5.
a
STI
p
-n+ n+ p+
b
STI
p
-n+ n+ p+
Fig. 3.4: Process flow of the modified CMOS process. Panel a) shows a cross section after well- and source/drain-implants and after deposition of the XP-oxide. Subsequently, openings are etched into the XP-oxide and gate dielectric as well as gate electrode are deposited and etched (b).
STI
p
-n+ n+ p+
SD Gate SD Substrate
Fig. 3.5: Cross section of a transistor processed with the modified CMOS process.
3.2.4 Deep Trench Capacitors with Metal Electrodes
In a typical trench DRAM cell the charge is stored in a single deep trench capacitor. Single devices can be connected only when a full process is used to fabricate the test structure.
Running a full process, however, is very expensive and not suitable for the development of the capacitor.
WB
BP
Fig. 3.6: Cross section of a deep trench short loop structure during processing showing deep trenches with oxide collar (grey), buried plate and buried well (hatched lines).
For this reason, so-called deep trench short loops (DTSL) are used where many trenches are connected in parallel. This process is very simple and allows for a short learning cycle.
At the beginning, deep trenches are etches into the silicon-substrate and a so-called oxide-collar formed at the upper part of the trench. Below the oxide-collar, the trench surface is doped with n-type species like Arsenic defining the substrate-electrode (buried plate) of