RTP-Oxides with the modified CMOS-process will be examined in this section in order to determine whether this process has an impact on the oxide properties. These samples can later on be used as a reference for metal gate transistors fabricated in the same way. During gate oxidation, source and drain are already doped which leads to a locally enhanced oxide growth. In Fig. 5.21 the CV-characteristics of capacitors with p-substrate (a) and n-substrate (b) are shown.
a)
121.0 Å Oxide; Substrate: 1*1020cm-3 34.0 Å Oxide; Substrate: 2*1016cm-3
b)
104.0 Å Oxide; Substrate: 5*1020cm-3 38.5 Å Oxide; Substrate: 5*1016cm-3
Fig. 5.21: CV-characteristics of capacitors fabricated using the modified CMOS-process for p-substrate (a) and n-substrate (b). Open symbols are measurement data while solid lines represent simulations.
Gate is n-doped with 8·1019 cm−3 for all structures. Extracted oxide thicknesses and substrate doping values are summarized in the legend and in Table 5.3.
Substrate p- n- p+ n+
Substrate Doping (cm−3) 2·1016 5·1016 1·1020 5·1020 Gate Doping (cm−3) 8·1019 8·1019 8·1019 8·1019
tox (˚A) 34.0 38.5 121.0 104.0
Table 5.3: Parameters of modified CMOS-structures extracted from CV-curves.
Oxide grows significantly thicker on highly doped substrates. The expected transistor structure of the modified CMOS process is sketched in Fig. 5.22. Oxide thickness is
5.6. SUMMARY 81
p-n+ n+
t
1t
2t
3Source Gate Drain
Fig. 5.22: Schematic of the modified CMOS structure as it is expected from the electrical data. Thick-nesses are t1 = 60 nm for the XP-oxide, t2 = 10 nm above source/drain and t3 = 3.5 nm for the gate oxide.
particularly large above source/drain, so that no breakdowns are expected in these regions during reliability analysis.
5.6 Summary
RTP-Tunnel-oxides that are used to study metal electrodes in Chapter 6 were character-ized in this chapter. It has been possible to extract physical oxide thicknesses of MOS-capacitors down to 25 ˚A in good agreement with ellipsometric measurements and leakage current analysis. The same results were gained for fully integrated samples and for simple planar capacitors so that the latter can well be used for basic characterization. Mod-elling of the leakage current through thin oxides has been greatly improved by including some additional physical effects and by assuming a variable effective electron mass at the silicon/silicon-oxide interface. Simulations of the leakage current for all voltages and all oxide thicknesses studied were in excellent agreement with experimental data. A higher interface state density as compared to furnace oxides was observed for the RTP-oxides, but was still low enough to use these dielectrics to analyze metal electrodes. Finally, the modified Cprocess has been characterized and showed no differences in MOS-properties compared to the standard CMOS-process. This technology can, therefore, be used to fabricate and study metal-gate transistors.
Chapter 6
Characterization of Metal Electrodes
This chapter describes electrical characterization of metal electrodes in MOS devices and their application to DRAM capacitors. Interface characteristics are studied on planar test structures with metal gate or substrate electrodes, respectively. Only metals that can be deposited in high aspect ratio trenches like CVD WSix and ALD TiN are suitable for DRAM application and have been investigated in this work. Limited thermal stability of metal gates on conventional dielectrics might require polysilicon/metal stacks to survive frontend temperatures. A polysilicon/TiN stack that can be integrated into a standard deep trench DRAM process was developed and is presented in the second half of this chapter.
6.1 Interface Characteristics of Metal Substrate Electrodes
Metal substrate electrodes for DRAM capacitors have the advantage that they lack a depletion region which further increases the overall capacitance. In addition, most metals under consideration have a higher work function than silicon and thus reduce the leakage current. For a specified maximum leakage current, the dielectric thickness can then be reduced which further increases the capacitance. For a successful integration, the substrate electrode has to support the defect healing process of the dielectric. Every dielectric has a certain density of defects right after deposition. Usually, plasma or thermal treatments are used to reduce the defect density before deposition of the top electrode. As described already in Section 4.1.1, silicon-rich WSix (x > 2.0) supports this process for standard NO [97]. In the following, test structures such as the ones mentioned in Section 3.2.1 with WSix as substrate electrode and NO as dielectric are characterized electrically. Fig. 6.1a shows capacitance-voltage curves of structures with three different WSix-compositions.
The gate is phosphorus-doped to a level of 1·1019 cm−3.
Equivalent dielectric thicknesses have been estimated from the accumulation capaci-tance at -3 V. Extracted values of 4.1-4.3 nm are around 0.5 nm lower than typical values from polysilicon electrodes which is attributed to the lack of a depletion region in the sub-strate. The trend towards smaller capacitance values for higher silicon to tungsten ratios suggests that a pure silicon layer might be formed at the WSix/NO interface during high-temperature treatment after deposition. For highest capacitance, silicon-rich WSix with a composition close to the thermally stable phase WSi2.0 will be most favorable. Also shown in Fig. 6.1a is the equivalent oxide thickness of a sample without surface passivation before NO-deposition as the one explained in Section 4.1.1. TEM-images show that the
equiva-83
a) WSix(x=2.3) w/o Passivation
Current(A/cm²)
Gate Voltage (V)
Fig. 6.1: Capacitance-voltage curves of MIS-capacitors with NO as dielectric and WSix of different composition as substrate electrode (a). Panel b) shows IV-characteristics of the same set of samples.
lent thickness increase is most likely due to oxide residuals at WSixgrain-boundaries. Fig.
6.1b shows IV-data of the same samples as in Panel a). Leakage currents do not change with WSix-composition and are well below the typical DRAM specification of 10−8A/cm2 at±1 V gate voltage. A reason for the increased leakage current of samples without passi-vation could be the existence of metal oxides at the grain boundaries which would increase the electric field locally. In summary, a WSi2.1-substrate electrode with passivation before NO-deposition satisfies the basic requirements for DRAM capacitors while increasing the capacitance by roughly 10%. Investigation of defect density and reliability values will be necessary to evaluate the process for further integration.