Metal Electrodes in Deep Trench Short Loops

The simplest approach to evaluate electrodes for deep trench applications are so-called DeepTrenchShort Loops (DTSLs - compare Chapter 3). One main advantage of metal deep trench fills compared to polysilicon is the low resistance. On the other hand it eases the integration process if the well-known properties of polysilicon as electrode could be used further. Hence, a stack of polysilicon and metal inside the DT seems to be most promising. Fig. 6.25 shows SEM-images of such a stack deposited into deep trenches after a 850^◦C anneal for 60 s in nitrogen. Similar images are gained for structures annealed at 1050^◦C.

a b c

Fig. 6.25: SEM-images of a polysilicon/metal-stack deposited into deep trenches after a 850^◦C anneal for 60 s in nitrogen. Panel a) shows an angled view of the wafer surface, Panel b) a cross section at the upper part of the trench and Panel c) a cross section at the bottom.

A smooth and thermally stable layer is observed in all parts of the trench. For elec-trical characterization, a special DTSL has been developed that enables to do all high-temperature processes before the deposition of the TiN. By this, capacitance and leakage currents can be studied for a large range of applied thermal budgets. Capacitors with a highly doped substrate electrodes were prepared as described in Fig. 6.26. Subsequently, the top electrode was structured in a way in which roughly 10⁶ trenches were switched in parallel. A sample with a conventional pure polysilicon-electrode has been processed for comparison. No significant changes in capacitance and leakage current were observed even at very high temperatures. In a second set of sample, temperatures were raised to 1050

◦C still leading to no degradation. This thermal budget is sufficient to fully integrate this material stack into a DRAM cell.

6.5 Summary

Metal substrate- and gate-electrodes have been investigated in this chapter. A tungsten-silicide substrate-electrode has been developed which supports the defect healing mech-anism of the standard NO and at the same time increases the capacitance and reduces the leakage current. Different gate-electrode materials have been tested and ALD-TiN has

6.5. SUMMARY 101

a)

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

0 5 10 15 20 25 30 35 40 45

Capacitance(fF/cell)

Node Voltage (V) 300 nm Poly

Poly/TiN - 850 °C Anneal Poly/TiN - 900 °C Anneal Poly/TiN - 950 °C Anneal Poly/TiN - 1000 °C Anneal

b)

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

10^-3 10^-2 10^-1 10⁰

Current(fA/cell)

Node Voltage (V) 300 nm Poly

Poly/TiN - 850 °C Anneal Poly/TiN - 900 °C Anneal Poly/TiN - 950 °C Anneal Poly/TiN - 1000 °C Anneal

Fig. 6.26: CV- and IV characteristics of deep trench short loop capacitors where roughly 10⁶trenches are switched in parallel. Capacitors have a highly doped substrate-electrode, NO as dielectric and a stack of 25 nm polysilicon and 15 nm TiN as top-electrode and were annealed at temperatures ranging from 850

◦C to 1000^◦C for 60 s in nitrogen.

been identified as a stable metal on thin oxides as well as on polysilicon. The characteriza-tion procedure developed in Chapter 2 was used on TiN-gate MOS-structures and revealed severe problems with the TiN-deposition process which were not seen directly by other means. Wafer signatures of extracted data were compared to marks on the deposition tool and enabled the identification of the core problem. This could finally be solved by modifying the deposition process enabling the fabrication of deep-trench short loops with polysilicon/TiN-electrodes suitable for deep-trench DRAMs.

Chapter 7

Conclusion

The main result of this study is the development of a full analysis procedure for metal-gate MOS-structures that allows to identify problems during processing and to extract physical parameters of metal electrodes. With knowledge gained from this analysis a polysilicon/TiN-stack has been developed and successfully integrated as low-resistance electrode into state-of-the-art deep trench DRAM-capacitors. These electrodes will be required to fabricate sub-100 nm deep trench DRAMs. The most important results can be summarized as follows:

7.1 Metal-Gate MOS-Structures

Parameters were gained from device simulations of MOS-capacitors that allow for an automatic extraction of flatband potential and physical oxide thickness. Physical oxide thicknesses were extracted from NMOS and PMOS devices with polysilicon and metal-gate electrodes within an accuracy of 1-2 ˚A when compared to ellipsometric measurements and IV-analysis. An improved model has been presented for the gate-leakage current describing the measurement data accurately for all voltages and for all gate oxide thicknesses under study.

To investigate these effects, a new test chip has been developed which enables the fabrication of metal-gate MOS-structures on short loops as well as on fully-integrated wafers. This test chip is now regularly employed to study extrinsic reliability properties of new gate dielectrics and electrodes on large-area capacitors. Intrinsic properties are investigated best on small-area structures. Therefore, a new measurement technique has been invented which enables capacitance-voltage measurements at very low capacitance levels.

A process technology has been developed which facilitates the fabrication of metal-gate MOS-structures even in the case that no dry etch process selective to the metal- gate-oxide is available. Encountered problems like XP-gate-oxide-thinning or gate-erosion during hard-mask removal were systematically solved and finally a method found out to analyze different metals as gate electrodes. While the deposition process of tungsten silicide leads to severe gate-oxide degradation, ALD-TiN was stable up to 800^◦C on SiO₂. The TiN-gate structures were then successfully used to characterize the TiN-ALD process, to identify process problems and to eliminate them.

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