Polysilicon Deposition on Metals

To integrate metal-electrodes into a DRAM trench capacitor, polysilicon has to be de-posited on metal. However, it is well known that metal-atoms can accelerate silicon deposition locally.

Fig. 4.27 shows an example of such effects for the polysilicon deposition on WSi_x. To inhibit the behavior demonstrated here, metal atoms at the surface of the WSi_x have to be passivated prior to polysilicon deposition. This has been reached by short nitridation or by room temperature oxidation for some hours.

a b c

Fig. 4.27: SEM-images of abnormal polysilicon deposition on WSix. Deposition rate is enhanced only locally (a) while the process runs normally in large areas in between (b). Locally, layer thicknesses are increased by as much as a factor of seven (c).

4.3 Summary

In this chapter, single processes as well as process integration have been developed which facilitate the electrical characterization of metal electrodes described in Chapter 6. Main focus has been directed at the fabrication of metal gate capacitors and transistors on the one hand and on the processing of metal-fill deep trench capacitors on the other.

Chapter 5

Characterization of RTP Tunnel-Oxides

In this chapter, RTP-oxides with thicknesses scaled down into the tunnel regime are ex-amined. In silicon process technology only furnace oxides are used as gate dielectric, since those have superior interface properties. RTP-oxides are usually employed as STI-passivation and as side wall oxide of the gate stack. For material characterization of electrodes, these oxides have the great advantage that splits in oxide thickness or gas com-position during growth can be conducted much more easily during processing. However, the characteristics of these oxides are not well known. Therefore, interface properties as well as breakdown behavior are studied in this chapter before characteristics of the metal electrodes are investigated in Chapter 6.

5.1 CV-Measurements on Tunnel-Oxides

If the thickness of tunnel oxides is larger than 20 ˚A, it can be extracted from CV-curves using the method described in Chapter 2. First, measurements on fully integrated wafers have been analyzed and compared with results from planar capacitors. Fig. 5.1 shows CV-curves of diffusion-limited capacitors with different oxide thicknesses.

a)

Fig. 5.1: CV-curves of fully integrated diffusion-limited capacitors with RTP-oxides of different thickness.

Open symbols are measurement data, while straight lines represent simulated capacitances. Parameters extracted from CV-curves are summarized in the legend. Oxide thicknesses are slightly higher for NMOS-structures (a) as compared to PMOS-capacitors (b).

To obtain best agreements, simulated curves had to be shifted by 60-80 mV. This indicates a polysilicon work function which is 60-80 meV lower than that of crystalline

67

silicon. The slightly higher oxide thicknesses in NMOS-structures (Panel a) as compared to PMOS-capacitors (Panel b) are due to the faster oxide growth rates on boron-doped substrates. Fig. 5.2 shows CV-data of STI-limited capacitors of the same wafers.

a)

Fig. 5.2: CV-curves of fully integrated STI-limited capacitors with RTP-oxides of different thickness.

Open symbols are measurement data, while straight lines represent simulated capacitances. Parameters extracted from CV-curves are summarized in the legend. Oxide thicknesses are slightly higher for NMOS-structures (a) as compared to PMOS-capacitors (b).

Substrate-doping can be extracted from CV-data in inversion, while the shape in ac-cumulation allows for an estimate of the gate-doping. Flatband potential and physical oxide thickness have been extracted with the method described in Chapter 2 and are summarized in Table 5.1.

Parameter NMOS (Diff) PMOS (Diff) NMOS (STI) PMOS (STI) Substrate Doping

(cm⁻³) 1.7·10¹⁷ 2.4·10¹⁷

Gate Doping

(cm⁻³) 2·10¹⁹ 5·10¹⁹ 2·10¹⁹ 5·10¹⁹

V_FB,1 (mV) -1106 1199 -1029 1198

V_FB,2 (mV) -1040 1153 -993 1164

V_FB,3 (mV) -991 1163 -991 1164

Table 5.1: Data of 4 different RTP-oxides as extracted from CV-curves. Flatband potential V_FB, and physical oxide thickness,t_ox, of diffusion-limited (Diff) and STI-limited (STI) capacitors have been exam-ined.

Apart from the thickest oxide of the NMOS-structure, both sets of data correlate well with each other, so that both structures are suitable for extraction of oxide thickness, t_ox, and flatband potential, V_FB. Automatically extracted oxide thicknesses are up to 1

˚A thicker than those values giving the best fit. This difference results from the influence of the gate-doping which has been neglected in Chapter 2. By extrapolation to 0 nm thickness, interface charge density and work function difference are extracted from the flatband potential. The dependence of the flatband potential on the oxide thickness is shown in Fig. 5.3.

A single value of a furnace oxide is shown for comparison. An interface charge density

5.1. CV-MEASUREMENTS ON TUNNEL-OXIDES 69

Fig. 5.3:Extracted flatband potential of RTP-oxides with different thickness of NMOS- (a) and PMOS- (b) capacitors. Closed symbols represent measurement data from STI-limited capacitors while open symbols show those of diffusion-limited structures. The straight line represents a linear fit. Given are extracted work function difference,φ_MS, and the interface charge density, N_f. A single value of a furnace oxide is shown for comparison.

extracted assuming an identical work function difference as for the RTP-oxide. The ac-curacy of this quantity, however, is limited since there was only one data point available.

Comparison to the RTP-oxide shows an interface charge density which is lower by a factor of 5. The flatband potential of PMOS-structures as function of oxide thickness exhibits a deviation from the usual linear behavior for thin oxides. This deviation, however, is not understood so far.

Fig. 5.4: CV-curves of simple planar capacitors with RTP-oxides of different thickness (a). Open symbols are measurement data while straight lines represent simulations. Panel (b) shows extracted values of the flatband potential for two lots. The straight line is a linear fit from which work function difference and interface charge density are extracted.

In the following, measurements on simple planar capacitors are analyzed to evaluate whether such samples are suitable for the extraction of parameters described so far. From a processing point of view, these structures are far easier and faster to fabricate, which shortens the learning cycle significantly. For even shorter processing times, only NMOS-capacitors were fabricated. Fig. 5.4 shows CV-data (a) and extracted values of the flatband potential (b) for two lots of planar capacitors with different oxide thicknesses.

Straight lines in (Panel a) are simulated CV-curves of lot A. Both sets of data correlate well with each other and yield an interface charge density which is around 20% higher than that for integrated samples. The value of the work function difference is lower by 150 mV due to the reduced substrate-doping of 1·10¹⁶cm⁻³. In summary, tunnel-oxides can well be characterized with the method shown in Chapter 2. Interface charge densities of

RTP-oxides are higher by a factor of 5 than those of furnace oxides, but are still sufficiently low to be used for the characterization of metal gate electrodes.