Logic criteria for glitch generation and propagation

Another source for glitch generation are gate-internal charge sharing effects. An example for a glitch generation due to charge sharing is given in Figure 22. When signal A rises, the internal

capacitances C₁, C₂ and C₃ are charged, resulting in a glitch at the output. The glitch peak volt-age at the output can be significant especially for small fanout capacitances (C_load). These glitches are not considered within this thesis.

In Chapter 3.2.3 the Boolean conditions for glitch generation and propagation are presented.

These Boolean conditions determine some logic properties for a glitch to be generated or prop-agated. Besides these logic properties the temporal relation of the colliding transitions deter-mine the dynamic properties of the glitch, which are discussed in Chapter 3.2.4.

may cause glitches. This later category of glitches should be eliminated by library designers.

However, if these glitches occur their power-consumption should be calculated correctly.

The following investigations will focus on glitches, which are caused by exactly two transi-tions. All known models (confer Chapter 4.2 and 5) can be extrapolated on glitches which are caused by more than two transitions by applying the model on pairs of consecutive transitions.

3.2.3.1 Glitch generation caused by two transitions

This subchapter deals with general gates first. Simplifications for special (monotonous) gates are derived afterwards.

Definition 10: Monotonous, non monotonous gates:

For a monotonous gate the direction of a potential output transition is unambiguously defined by the direction of the causing input transition.

Examples for monotonous gates are AND-, NAND-, OR- and NOR-gates. An EXOR-gate is an example for a non monotonous gate.

Definition 11: Inverting and non inverting monotonous gates:

Inverting and non inverting monotonous gates are further distinguished.

For inverting gates a rising (falling) input transition causes a falling (rising) output transition (e.g. NAND and NOR gates). For non inverting gates a rising (falling) input transition causes a rising (falling) output transition (e.g. AND and OR gates).

Definition 12: Monotonous primitive gates:

For monotonous primitive gates the input assignment is free from the functional point of view. Such gates’ pull down respectively pull up networks either consist of transistors in series or in parallel. All AND-, OR-, NAND- and NOR-gates are monotonous primitive gates.

a) General Gates

Logical criteria for glitch-generation are introduced here. It is assumed for all cases that two input signals transitions x_i and x_j at two different inputs collide in such a way, that a glitch is possible (from the timing point of view). Two different sorts of glitches are distinguished:

• a transition at input i causes a falling edge at the output and a transition at input j causes a ris-ing edge or

Figure 23:Example for glitch generation and propagation.

t V

generation propagation

t V

t V

t V

t V

• a transition at input i causes a rising edge at the output and a transition at input j causes a fall-ing edge.

The first sort of glitches is called VDD-VMIN-VDD-glitch and the other is called VSS-VMAX-VSS-glitch.

For simplicity logical events from 0 to 1 and vice versa are associated with the two input tran-sitions. In the following equations some terms are used, which are now defined:

symbol meaning

i, j Inputs of an arbitrary gate, at which two colliding transitions occur.

x_i(t), x_j(t) Signal at input i respectively j as a function of time.

x(t) The whole input vector as a function of time.

t_i, t_j Instant, when a logical event of input i respectively j occurs.

x_i, x_j Value, at an input (time independent); value may be a Boolean represen-tation of a voltage.

- Don’t care: the respective variable is removed from the Boolean expres-sion f(x(t)). E.g.:

f(x(t)) Boolean Function of the investigated gate.

t_i^-, t_i⁺, t_j^-, t_j⁺ The instant immediately before (after) the event t_i respectively t_j is denoted with the superscript - (+).

, Negation of Boolean function respectively value.

x_iHL(t_i), x_iLH(t_i) Signal x_i performs a High->Low respectively Low->High transition at time t_i.

f x( ) = x₂∧x₁∧x₀ f x( ) = x₁⊕x₀

f x( ) _x

1=- = x₂∧x₀ f x( )

x₁=- = x₀

f x( ) x_i

The logical behaviour can be expressed by a Boolean equation as follows:

(9)

(10)

This Boolean expression cannot be transformed into a Boolean difference in general because it has to be ensured that x_i causes a transition at the output opposite to that of x_j.

Definition 13: Boolean difference:

The Boolean difference defines the condition for f(x) to be sensitive on a Gl

f x t( ( ) ^-_i )∧f x t( ( )⁺_i )

( )

x_j=-; x_i( )t_i^- =x_i( )t_i⁺

falling slope caused by event at x_i

∧ f x t( ( ) ^-_j )∧f x t( ( )⁺_j )

( )

x_i=-; x_j( )t_j^- =x_j( )t_j⁺

rising slope caused by event at x_j

∨ f x t( ( ) ^-_i )∧f x t( ( )⁺_i )

( )

x_j=-; x_i( )t_i^- =x_i( )t_i⁺

rising slope caused by event at x_i

∧ f x t( ( ) ^-_j )∧f x t( ( )⁺_j )

( )

x_i=-; x_j( )t_j^- =x_j( )t_j⁺

falling slope caused by event at x_j

=

Gl

x_iHL( )t_i f x( ) _x

i=1 f x( ) _x

i=0

∧ ∧

x_i = falling⇒f x( ) = falling

x_iLH( )t_i f x( ) _x

i=0 f x( ) _x

i=1

∧ ∧

x_i = rising⇒f x( ) = falling

∨

 

 

 

 

x_j=

∧ x_jLH( )t_j f x( )

x_j=0 f x( )

x_j=1

∧ ∧

x_j =rising⇒fx = rising

x_jHL( )t_j f x( )

x_j=1 f x( )

x_j=0

∧ ∧

x_j = falling⇒fx = rising

∨

 

 

 

 

x_i=

∨ x_iLH( )t_i f x( )

x_i=0 f x( )

x_i=1

∧ ∧

x_i =rising⇒fx = rising

x_iHL( )t_i f x( )

x_i=1 f x( )

x_i=0

∧ ∧

x_i = falling⇒fx = rising

∨

 

 

 

 

x_j=

∧ x_jHL( )t_j f x( )

x_j=1 f x( )

x_j=0

∧ ∧

x_j = falling⇒f x( ) = falling

x_jLH( )t_j f x( )

x_j=0 f x( )

x_j=1

∧ ∧

x_j =rising ⇒f x( ) = falling

∨

 

 

 

 

x_i =

-=

                         

                         

                         

                         

change of input x_i:

The Boolean differences and are necessary but not sufficient conditions for a glitch. Equation 10 can be simplified for monotonous gates.

b) Monotonous gates

For monotonous gates the direction of an input transition unambiguously defines the direction of a possible resulting output transition. Consequently only one term per line of Equation 10 remains.

For inverting monotonous gates (e.g., single stage gates) the terms for falling (rising) output-slopes which are caused by falling (rising) input-output-slopes are always logically zero. For non inverting monotonous gates the rising (falling) output-slopes which are caused by falling (ris-ing) input-slopes are impossible. Hence Equation 10 can be simplified for inverting monoto-nous gates as follows:

(11)

The terms and are both false for inverting monotonous gates. Hence Equation 11 can be modified as follows:

(12)

Equation 12 also holds for non inverting monotonous gates.

c) Monotonous primitive gates

For monotonous primitive gates Equation 12 can be further simplified:

(13)

Combining Equations 12 and 13 the following relation can be derived:

f x( )

∂ x_i

---∂ f x( )

xi=0 f x( )

xi=1

⊕

= f x( )

∂ x_i ---∂

x_j=

-f x( )

∂ x_j ---∂

x_i=

-Gl f x( )

x_i=0 f x( )

x_i=1

∧

[ ]

x_j=

-f x( )

x_j=1 f x( )

x_j=0

∧

[ ]

x_i=

-∧ ∧

x_iHL( )t_i ∧x_jLH( )t_j ∨x_iLH( )t_i ∧x_jHL( )t_j

[ ]

=

f x( )

x_i=1 f x( )

x_i=0

∧

[ ] f x( )

x_j=0 f x( )

x_j=1

∧

[ ]

Gl f x( )

x_i=0 f x( )

x_i=1

⊕

[ ]

x_j=

-f x( )

x_j=1 f x( )

x_j=0

⊕

[ ]

x_i=

-∧ ∧

x_iHL( )t_i ∧x_jLH( )t_j ∨x_iLH( )t_i ∧x_jHL( )t_j

[ ]

=

f x( )

x_i=1

( )

xj =

-f x( )

x_j=1

( )

xi=

-= f x( ) _x

i=0

( )

x_j =

-f x( ) _x

j=0

( )

x_i=

-=

(14) All monotonous primitive gates only have either one minterm or one maxterm. Hence the Boolean difference within Equation 14 consists of one minterm only. I.e., that a glitch can only be caused by the following input transitions:

• input x_i falls and input x_j rises or

• input x_i rises and input x_j falls.

One of the glitch causing input-signals of monotonous primitive gates always changes

• from a logically controlling to a logically non-controlling signal and

• the other input-signal from a logically non-controlling to a logically controlling signal.

Definition 14: Controlling and non-controlling signal:

An input value x_i is controlling the output, if the Boolean difference of all other inputs is FALSE:

If this property is not fulfilled, x_i is a non-controlling input value.

A controlling input value clearly defines the output value f(x).

Example NAND gate: the value 0 is a controlling input value (output = 1):

(15)

I.e., that before and after the glitch the gate is driven by a controlling input-pattern. Hence for monotonous primitive gates glitches can only be generated at either logical high- or low-level.

In particular this means for the following gates:

3.2.3.2 Glitch propagation caused by two transitions

Glitches or hazards at a single input pin may be caused by either hazards or glitches of the driving gate. It is assumed, that two consecutive input signal transitions at the same input

col-gate only possible generated glitches

NAND VDD-VMIN-VDD glitch

AND VSS-VMAX-VSS glitch

NOR VSS-VMAX-VSS glitch

OR VDD-VMIN-VDD glitch

Gl [x_iHL( )t_i ∧x_jLH( )t_j ∨x_iLH( )t_i ∧x_jHL( )t_j ] f x( )

x_i=0 f x( )

x_i=1

⊕

[ ]

x_j=

-∧

=

∂f x( )

∂x_n

---x_i={ , }0 1 ( ),n≠i

≡0⇒x_i controls f x( )

f x( ) x_j

∏

n

=

∂f x( )

∂x_n

---xi={ , }0 1 ( ),n≠i

f x( )

x_i=0,x_n=0 f x( )

x_i=0,x_n=1

⊕ 1⊕1 0

= = =

lide in such a way, that a glitch is possible (from the timing point of view). The logical crite-rion for a glitch propagation is, that the Boolean difference (x_i is the causing input-pin) is TRUE.

Im Dokument Accurate power analysis of integrated CMOS circuits on gate level (Seite 44-50)