7.2 General simulation algorithm
7.2.2 Event driven simulation algorithm
Within conventional simulation algorithms, events are scheduled for the time, a library defined logic threshold voltage is crossed and the signal change is modelled as a sharp edge (refer to Chapter 4.2). The slowly changing voltage-waveform of the signal, which lies behind this model, is not considered. As long as the real signal is between VSS and VDD, a possible addi-tional input event might lead to a glitch at a gate’s output event. Therefore the signal output waveforms are modelled as linear approximated ramps (confer Figure 84).
The ramp is represented by two events:
• the begin event and
next valuecurrent value 0 1 X L H
0 - fall (fall) - fall
1 rise - (rise) rise
-X (rise) (fall) - (rise) (fall)
L - fall (fall) - fall
H rise - (rise) rise
-Table 15:Mapping of all possible transitions in the 5 value system on rising (rise), falling(fall) and no transition(-) (transitions which are written in brackets are considered as transitions with 50% probability).
Figure 84:Modelling of signal changes.
VSS VDD
t V
VH
1*
2* 3*
1*: conventionally modelled voltage waveform as a sharp edge 2*: real voltage waveform
3*: modelled ramp waveform
• the end event.
The first is the begin event for the instant when the ramp becomes active. When the begin event is processed by the simulator the ramp is queued again as an end event for the instant when the ramp becomes inactive. The term active refers to the time, during which the modelled voltage-waveform is between VSS and VDD for single transitions. In case of glitches the active part of a ramp is defined by the period, it describes the voltage waveform of the glitch. E.g. in Figure85 the active parts of the output ramps are indicated by the bold part of the solid lines.
I.e., the instant when a ramp becomes active is either
• the time when leaving VDD respectively VSS or
• in case of a resetting ramp as part of a glitch the time when crossing the setting ramp.
The deactivation of a ramp takes place either
• when reaching VDD respectively VSS or
• in case of a setting ramp as part of a glitch when crossing the resetting ramp.
Figure 85:Ramp handling within local output event queues.
Figure 86:Event handling within local queues of a gate.
V(b) V(c)
V(c)
t BI-ramp 1
BI-ramp 2 EI-ramp 1
BI-ramp 3 EI-ramp 2
EI-ramp 3
V(a)
BI: Begin-Instant EI: End-Instant VDD
a
b
c local queue of a
local queue of b
local queue of c no costly glitch
han-dling is needed for the local input queues!
For the three ramps of the example in Figure 85 the begin events and end events are indicated by BI-ramp n respectively EI-ramp n (n={1,2,3}).
Generally the simulation algorithm is based on two types of event queues:
• local event queues: for a signal all events are organized within its local queue,
• global event queues: the global event queue ensures the execution of the events from the local event queues in the right time order.
For input and output pins local event queues are used (confer Figure 86). Actually two separate global event queues are implemented for input events and output events.
Figure 87:Flowchart of the basic simulation algorithm.
Initialization
Get next simulation time
Recalculate the logic states for the current instance
Input Events?
new O.
Events?
Check for glitches
Glitches?
Glitch handling
Scheduling of output events
yes
yes
yes no no
Output Events?
Schedule end event into queues
begin Event?
Propagate to fanout input pins and put into queues no
yes
yes
Remove output event from local queue
Stop simul.
yes
no End of simulation
no
no
The general simulation algorithm is described by the flowchart in Figure 87. After initializa-tion of the circuit, the first simulainitializa-tion time is read from the global event queues.
For that simulation time all input events are processed first. For each input transition the new signal value is assigned (one at a time) to the input and the gate behaviour is recalculated. In case of a new event it must be checked, whether the new event is a resetting event of a glitch.
In case of a glitch, the glitch handling algorithms must be applied to correctly consider the dynamic scheduling time and glitch peak voltage. The new output event is then scheduled into the respective local and global output queues. As soon as no further input event is pending for the current simulation time, all output events are processed next.
Begin events at a gate’s output-queue(s) are scheduled into the input queues of driven input pins of consecutive gates. The event time is the Begin-Instant of the ramp. To properly repre-sent the ramp each event holds the following attributes: the slope, the start- and end-voltage. If the presented output event is not a begin event, it is simply removed from the local queue.
After processing all events for the current simulation time, the next simulation time is read from the global event queues. As begin events at a gate’s output have been propagated to fanout input queues, the described flow is typically run once more for the same simulation time.
The simulation continues until a user defined stopping criterion, which is not further discussed here, is satisfied.
In causal systems the transfer through a physical gate is always delayed. As the actual logic evaluation is done when processing a begin event of an input, it cannot have an impact before that instant. When choosing other predefined logic threshold voltages for events, negative delays may result for conventional simulation algorithms (confer Chapter 3.2.1). As the pro-posed simulation algorithm is intended to model this physical behaviour accurately, delays lower or equal to zero can not occur. If such cases occur during simulation, they are based on inaccurate delay characterization data and can be set to zero.