Colliding and non-monotonous signal changes

• analytical equations,

• table look up approaches.

The parameters of analytical equations are typically derived directly from basic semiconductor equations in conjunction with technology informations or detailed circuit-level simulation results [West93].

The table look up approach is based on a number of circuit-level simulations with varying fanout capacitances and input slopes for each delay path. The characterized values can be applied to interpolation procedures in order to obtain delays and output slopes for fanout capacitances and input slopes which are not explicitly characterized. The interpolation is typi-cally needed as it is not possible to characterize each pair of possible fanout capacitances and input slopes.

The advantage of using analytical equations is, that no explicit characterization of each library cell is needed. The table look up approach requires a characterization of each library cell with possible derating factors for process-, temperature- and supply voltage variations. However, if this characterization data is available, the calculation of the instance dependent delay calcula-tions are typically faster and more accurate than the delays, which are calculated from analyti-cal equations. Within this thesis a table look up approach is applied to simulation.

Figure 20:Example of a voltage waveform inside a 16x16bit multiplier (c6288).

Figure 21:Example for a glitch: Two colliding input transitions result in a glitch (the non-col-liding output waveforms are also plotted in the lower graph).

0 1 2 3 4 5

4e-09 5e-09 6e-09 7e-09 8e-09 9e-09 1e-08 1.1e-08 1.2e-08 1.3e-08 1.4e-08

voltage [V]

time [s]

glitch output waveform non colliding setting output waveform non colliding resetting output waveform 0

1 2 3 4 5

voltage [V]

setting input waveform resetting input waveform

A B

Y

• speed-up transition - the output transition is faster, if it is caused by multiple input transitions instead of a single one - and

• slow-down transition - the output transition is slower, if it is caused by multiple input transi-tions instead of a single one.

Speed-up transitions, which are caused by two colliding input signals, generally occur, if the output signal transition only requires one of the two input signals to change (with the other remaining constant at the initial signal value). The structural condition is simply, that two par-allel transistors are both turned on, which lowers the effective resistance for charging respec-tively discharging capacitances.

Slow-down transitions, which are caused by two colliding input signals, generally occur, if the change of the output signal requires both signal transitions. Hence, the structural condition requires two transistors in series to be turned on.

The most important of the above mentioned three collision effects from the power estimation’s point of view are glitches and hazards. In Figure 21 an example for a glitch at a NAND2 gate’s output is given. The glitch is generated by two input transitions in opposite directions. The set-ting input transition (rising) at input B causes the output voltage to drop. The falling resetset-ting input transition at input A causes the output voltage to return to its initial value.

Definition 9: Setting and resetting transition:

In case of a glitch generation or propagation, the setting input transition causes the first output transition and the resetting input transition causes the second output transition. The two output transitions have opposite directions.

Besides the glitch-waveform, the figure also contains the complete output-waveforms which would result from one input transition, if the other input signal is stable at 1 (respectively at V_DD). The glitch waveform is equivalent to the complete setting output-waveform until the resetting input-waveform becomes important. Afterwards the resetting input transition (input A) starts controlling the glitch waveform. As the voltage of the output waveform is higher than V_SS when the resetting input starts controlling the glitch, the fanout capacitances and the cell internal capacitances only need to be partly charged respectively discharged. As a consequence the resetting part of the glitch waveform is delayed less than the corresponding voltage levels of the non-colliding resetting output waveform. This delay reduction has a significant impact on signal propagation through consecutive gates, which are sensible to the glitching input sig-nal.

An input collision which results in a hazard simply slows down the first (complete) output transition, because the second input transition has an opposite logical impact on the output.

The second output transition is possibly influenced by the setting input transition, because the end of the setting input transition has not necessarily been reached when the resetting input transition starts influencing the output waveform. In conclusion, the hazard’s peak voltage waveform is less steep.

Within this work the contribution to glitches which are caused by cross-talk is not dealt with.

Even though it should be mentioned that the influence of cross-talk on power consumption will increase with the growing number of metal layers, growing aspect ratios (height/width of metal lines) decreasing metal pitches and the enhancing chip complexity due to shrinking transistor sizes growing die sizes.

Another source for glitch generation are gate-internal charge sharing effects. An example for a glitch generation due to charge sharing is given in Figure 22. When signal A rises, the internal

capacitances C₁, C₂ and C₃ are charged, resulting in a glitch at the output. The glitch peak volt-age at the output can be significant especially for small fanout capacitances (C_load). These glitches are not considered within this thesis.

In Chapter 3.2.3 the Boolean conditions for glitch generation and propagation are presented.

These Boolean conditions determine some logic properties for a glitch to be generated or prop-agated. Besides these logic properties the temporal relation of the colliding transitions deter-mine the dynamic properties of the glitch, which are discussed in Chapter 3.2.4.