3.5 Dynamic power consumption
3.5.2 Capacitive power consumption
• the capacities between the switching input pin and the output pin is charged by a voltage-swing of 2-times VDD and
• all gate-capacities of the pull up network (for the NOR-3 cell) are at least completely charged respectively discharged
For a rising output-slope of the NOR3-cell, the n-transistors’ drain-voltage of the switching transistor is at VSS before the transition and at VDD afterwards. Hence the gate-drain capaci-tance (Miller capacicapaci-tance) of the switching transistor is charged with a voltage swing of 2*VDD. Similarly the drain of the switching p-transistor is charged by a swing of 2*VDD respectively 2*VDD-VT.
The maximum possible range of fanin capacitances is between 30fF and 48.5fF. I.e., if the worst case (i.e. maximum) capacitance is taken as a fixed fanin capacitance the actual capaci-tance may be up to 38% lower for some cases. This large deviation is important for power and delay calculation. As a fixed value is typically taken for the fanout load of a gate, this is a source of error when comparing gate level simulation results to circuit level simulation results.
However, for future designs the contribution of input capacitances to the total fanout capaci-tance of a gate is decreasing [Veen98].
From the power consumption’s point of view, it is also important, that a changing internal node voltage may results in charge flow through not transitioning input pins. An example is given within the above discussed NOR3 testcase. At 100 ns (confer Figure 39) a falling transi-tion is applied to input in2. Consequently node_5 and node_8 are connected to VDD and the voltage rises. Hence the gate-drain and the gate-source capacitances of T4 are charged.
The exact fanin capacitance for delay determination and power calculation is hard to obtain.
The reason is, that the fanin capacitance is typically considered as part of the fanout capaci-tance of a driving gate. This has the following implication for a correct modelling of fanout capacitances:
• The correct consideration of all consecutive gates’ fanin capacitances as part of a fanout capacitance requires the knowledge of all node voltages (internal and external) of the driven gates,
• the fanin capacitance’s contribution to a fanout capacitance cannot be determined a priori, as the node voltages of consecutive gate’s are not constant and consequently the fanout capaci-tance needs to be calculated on the fly.
Even if a simulator allows the evaluation of signals in consecutive gates, the consideration of these signals requires a lot of effort and would undoubtedly significantly slow down the simu-lation.
In conclusion it has to be kept in mind, that the fanin contribution to a gate’s fanout capaci-tance may vary significantly (up to approximately 38% for the analysed example, if the maxi-mum fanin capacitance is characterized). From the power consumption’s point of view, charges through an input pin may even be caused by transitions at other input pins. Within the library characterization, which was needed for the simulator GliPS, the worst case fanin capac-itances were characterized (switching output).
Capacitive power is consumed, if the voltage over a capacitance changes. A simple switch model of a single CMOS stage is illustrated in Figure 40. The MOS transistors are each
replaced by a switch and a resistor. The pull up (pull down) switch is open (closed) before t0 and closes (opens) for a period ∆t at t = t0. This causes the output voltage Vout(t) to rise from 0 to ∆V. Hence, the charge flow Q can be calculated as follows:
(20) The total energy, which is supplied by the voltage source, is given by
. (21)
Part of the energy is stored within the capacitance Cfanout (Encap) and part of it is turned into heat within the pull up resistance (ERpullup):
(22)
At t = t0+∆t the pull up switch is opened and the pull down switch is closed again. The energy Encap, which was previously stored within the fanout capacitance, is now turned into heat within the pull down resistance (EnRpulldown).
(23) Hence during a whole cycle the energy En (Equation 21) is drawn from the voltage source and turned into heat.
For a complete VDD swing (|∆V| = VDD) the energy Encap, EnRpullup and EnRpulldown are equivalent:
Figure 40:Switch modelling of a CMOS stage.
t < t0
Cfanout VDD
Vout(t)
t = t0
Cfanout VDD
Vout(t)
t > = t0+∆t
Cfanout VDD
Vout(t)
RPullup RPullup RPullup
RPulldown RPulldown RPulldown
Q = Cfanout⋅ ∆V
En = Q V⋅ DD = Cfanout⋅ ∆V ⋅VDD
Encap 1
2--- ⋅Cfanout⋅∆V2
=
E nRpullup Cfanout⋅ ∆V ⋅VDD 1
2---⋅Cfanout⋅∆V2
– Cfanout ∆V2 VDD
---∆V 1 2
--- –
⋅ ⋅
= =
E nRpulldown 1
2--- ⋅Cfanout⋅∆V2
=
(24) The actual energy, which is turned into heat respectively drawn from the voltage supply for charging and discharging the fanout capacitance, is equivalent to
. (25)
According to the above discussion, the energy consumption of this whole cycle can approxi-mately be divided into two equal parts which are associated with each voltage swing ∆V:
(26) This equation can also be applied to calculate the capacitive energy consumption of more gen-eral waveforms (confer Figure 41).
The energy, which is consumed during a given period τ is given by:
(27) The term is the sum of all voltage changes within the period T.
The capacitive power calculation is straight forward:
(28) Figure 41:Example for a dynamic glitch.
E nRpullup
∆V=VDD Encap
∆V=VDD E nRpulldown
∆V=VDD
1
2--- ⋅Cfanout⋅VDD2
= = =
En = EnRpullup+E nRpulldown = Cfanout⋅ ∆V ⋅VDD
E nRpullup E nRpulldown 1
2--- ⋅Cfanout⋅ ∆V ⋅VDD
≈ ≈
∆V1
∆V3
∆V2
voltage [V]
t [s]
E n 1
2--- Cfanout VDD ∆Vi
i=1
∑
3⋅ ⋅ ⋅
=
E n 1
2--- Cfanout VDD ∆Vi
∑
T⋅ ⋅ ⋅ 1
2--- Cfanout VDD2 ∆Vi VDD
---∑
τ⋅ ⋅ ⋅
= =
∆Vi
∑
TPCap 1
2--- VDD Cfanout
∆Vi
i
∑
---τ
τlim→∞
⋅ ⋅ ⋅
=
Let α be the average number of transitions within one clock cycle (glitches are counted accord-ing to their fractional voltage swaccord-ing with respect to VDD):
(29) The sum respectively the term α can be obtained by logic simulation over a sufficient time-interval (confer Chapter 4.1.4) using an appropriate model. By combining Equations 28 and 29, the following common term for capacitive power consumption is obtained:
(30)
• α is the average number of transitions within one clock cycle,
• f is the clock frequency and
• Ceff is the effective switched capacitance per clock cycle (unit is F).
The capacitive power consumption of a complete integrated circuit or a specific part of it is calculated by summing up the power consumption of each capacitive contributor:
(31) Sometimes the term effective capacitance is defined to represent the total switched capacitance of the analysed part of the circuit (i.e. ). However, here the definition is used as intro-duced above.
Within this thesis high emphasis is put on correctly considering glitches for power calculation.
Therefore the partial voltage swings must be considered in the power formula.