3.5 Dynamic power consumption
3.5.1 Determination of capacitances
The lumped capacitance Cfanout basically consists of consecutive gate’s fanin capacitances, diffusion capacitances of the drain regions connected to the output and interconnection (rout-ing) capacitances.
The interconnection capacitance may approximately be regarded as a fixed capacitance, which can be extracted from layout. Fringing fields, that occur at the edges of the conductor due to its finite thickness, may degrade accuracy [West93]. The accurate extraction of capacitances between wires on the same layer is also a complicated task. As within delay and power models these capacitances are lumped into capacitances towards VSS, some inaccuracies result from cross talk capacitances, if the signals of coupled interconnects change simultaneously in the same direction.
Besides the interconnection capacitance the fanin capacitances (of consecutive gates) contrib-ute to the fanout capacitances. The physical device capacitances of MOS transistors depend on their operation points, as the channels may only serve as plates within the capacitance model, if the channels actually exist. I.e., during a transition the capacitance, which a driving gate has to
charge respectively discharge, is varying during the transition, which impacts the driver’s out-put waveform and as a consequence its delay [West93].
The variation of fanin capacitances have been investigated by means of circuit level simula-tion. The characterization/testbench is introduced now. Within fanin characterization two dif-ferent methodologies are distinguished (confer Figure 37):
• Current Measurement: the charge through the input terminal is measured (circuit level simu-lation) and divided by VDD,
• Delay Measurement: the fanin capacitance is derived from delay measurements of an arbi-trary gate for different fanout loads:
- large fanout capacitor Clarge, - small fanout capacitor Csmall, - the gate’s input pin under test.
For the delay measurement method it is assumed, that a linear relation between the gate’s fanout capacitance and its delay exists. Hence the delay measurement of two known fanout capacitances defines the parameter of a linear function. After measuring the delay of the gate’s input under test, the corresponding (effective) fanin capacitance can be read from the diagram (confer Figure 37) respectively calculated from the functional description.
The two alternative characterization methods deliver different results. The current measure-ment method is best suited for power characterization and the delay measuremeasure-ment method is Figure 36:The two lumped capacitance towards VDD and VSS may be joined.
n QSC+QCapIntern
QCapVSS
Qin
QCapVDD
n QSC+QCapIntern
QCap
Qin
n QSC+QCapIntern
Qin
QCap n
QSC+QCapIntern QCapVDD
Qin
QCapVSS CfanoutVSS CfanoutVDD
CfanoutVSS CfanoutVDD
Cfanout
Cfanout Cfanout= CfanoutVSS+ CfanoutVDD
best suited for delay characterization. Within this thesis the current measurement method is used for the testbench of the following fanin capacitance analysis and library characterization.
Besides these physical variations of the fanin capacitance, the simple black box approach assumes a constant fanin capacitance, which is lumped towards a fixed potential (typically VSS, confer right part of Figure 36). The voltage swing across the actual physical capacitances commonly differs from VDD. The exact voltage swings depend on the state of other transistors, which are part of the CMOS stage, and possibly their history. These effects are exemplified using the NOR3-cell transistor schematic, which is shown in Figure 38. This model includes capacitances between almost each pair of nodes. The sizes of the capacitances are derived from layout extraction.
A very big portion of the internal capacitances results from the connection of the various tran-sistors on the diffusion layer. The diffusion can be modelled as a diode that is commonly not conducting, i.e. the diodes behave like non-linear capacitances. The capacitances CT2, CT 4, CoutVSS and CoutVDD mainly consist of these connection-diffusion-diodes. The gate-capacities of the MOS transistors are covered by the transistor-models.
For this discussion the following assumptions are made:
• a transition at a cell’s output is caused by a transition of a single input pin (i.e. glitches are not taken into account)
Figure 37:Fanin characterization methods.
VDD or VSS τG
τCSmall Csmall
Clarge τCLarge
C τ
CSmall Cfanin CLarge τCLarge
τG τCSmall VDD or VSS
A Cfanin
I td
∫
VDD
---=
Current Measurement Delay Measurement
• the voltages at the inputs are always VDD or VSS when they are in a steady state,
• the voltage VDD and VSS is constant over time and
• each instance of a circuit is supplied with the same voltage.
To assess the relevance of different effects, the fanin capacitance of a NOR3-cell’s input pin in2 is analysed in detail (confer Figure 38). The cell is taken from an industrial library of an 800nm technology. The fanin-capacity is specified with 41fF in the library datasheets. In Figure 39 the voltage at the internal nodes node_5 and node_8 is shown for different situations.
Neither of these 6 situations (confer Figure 39) leads to a transition at the output. Under these conditions the fanin-capacity varies up to 30% and hence needs further consideration.
The total fanin-capacity can be divided into three components:
• fanin capacity of the n-block (pull down network),
• fanin capacity of the p-block (pull up network) and
• cross capacity towards the other input pins.
These contributions are observed by measuring the charge through the VDD-, the VSS- and the input pin-terminals within the SPICE simulation.
For the n-block contribution of this example only the transistor T3 is switching. Both, Vout and of course VSS are constant for these 6 situations. Hence the drain- and source-voltage of T3 is not changing and its contribution to the total fanin-capacity is the same for each case (16.5fF).
During the first two transitions of in2 the transistors T2 and T6 are not conducting and hence node_5 and node_8 are only coupled with VDD via CT2 and CT4 while T4 is switched off. The rising input slope at 20ns raises the voltage in the channel and at node_5 and node_8 up to about 5.5V - a higher voltage is not possible because the diffusion-diodes will start conducting.
This voltage-level slowly decreases to a stable value of about 5.3 V and the gate capacity remains partly charged. The falling input slope at 40ns draws the voltage at node_5 and node_8 immediately down to about 3.9V. Hence the gate-capacity is not discharged com-pletely. Cfanin respectively the contribution of the capacity towards VDD is about 4.5fF smaller Figure 38:Transistor schematic of a NOR3-cell.
in1 in2 in3
VDD
VSS
T1 T3 T5
T2
T4
T6
out CoutVDD
CoutVSS Cin3VSS
Cin3out
Cin2VSS Cin2out
Cin1VSS
Cin1out
CT 4 CT 2
Cin3VDD Cin1VDD
Cin2VDD
Cin2_in1
Cin3_in2
node_5
node_8
than for the rising slope at 20ns. It has to be noted, that the situation before 20ns (all p-transis-tors turned off and 5V at node_5 and node_8) cannot be reached during operation. If a node is isolated from VDD by a transistor turning off, its voltage is drawn down by the falling input-slope and hence its voltage is always lower than VDD. This situation only occurred due to the static initialization by the circuit level simulator at 0ns.
During the transition of in2 at 120ns and 140ns the transistor T2 is conducting and T6 is not.
The voltage-swing of node_8 is the same as before at 20ns. The falling transition draws the voltage at node_8 down for a short period (until the channel of T4 is build up). Because the voltages at node_5 and node_8 are the same before the rising and after the falling slopes, all measured capacities are the same.
During the transition of in2 at 220ns and 240ns the transistor T6 is connecting the output with node_8 and T2 is not conducting. The capacities measured for these transitions are much smaller than before. This is due to the non-linear gate-capacity, which is much smaller if the voltage-level in the channel is less than VDD. The total fanin’s contribution towards VDD is very small, because only the gate-source-capacity of T4 is discharged via VDD and the gate-drain-capacity not.
If an other input (in1 or in3) toggles, the number of differing voltage-combinations at source-and drain is much smaller. Hence the fanin-capacities almost don’t vary at all.
The capacitances between the inputs are given in the last row of Figure 39. They don’t vary significantly for different cases.
All situations, that have been discussed so far, don’t result in a transition at the output of the cell. The fanin-loads of the switching NOR3-cell are significantly higher (48.5fF for in2) for the following reasons:
Figure 39:Fanin-Capacities in dependence of different internal situations.
V(node_8) V(node_5)
V(in2) rising falling rising falling rising falling
V(in1) VDD VDD VSS VSS VDD VDD
V(in3) VDD VDD VDD VDD VSS VSS
fanin- Capacitan-ces in fF
total 40.5 36 40.5 40.5 30.5 30
to VDD 17.5 13 16 16 5.5 7
to VSS 16.5 16.5 16.5 16.5 16.5 16.5
to in1+in3 7 8 6 6 6.5 6.5
• the capacities between the switching input pin and the output pin is charged by a voltage-swing of 2-times VDD and
• all gate-capacities of the pull up network (for the NOR-3 cell) are at least completely charged respectively discharged
For a rising output-slope of the NOR3-cell, the n-transistors’ drain-voltage of the switching transistor is at VSS before the transition and at VDD afterwards. Hence the gate-drain capaci-tance (Miller capacicapaci-tance) of the switching transistor is charged with a voltage swing of 2*VDD. Similarly the drain of the switching p-transistor is charged by a swing of 2*VDD respectively 2*VDD-VT.
The maximum possible range of fanin capacitances is between 30fF and 48.5fF. I.e., if the worst case (i.e. maximum) capacitance is taken as a fixed fanin capacitance the actual capaci-tance may be up to 38% lower for some cases. This large deviation is important for power and delay calculation. As a fixed value is typically taken for the fanout load of a gate, this is a source of error when comparing gate level simulation results to circuit level simulation results.
However, for future designs the contribution of input capacitances to the total fanout capaci-tance of a gate is decreasing [Veen98].
From the power consumption’s point of view, it is also important, that a changing internal node voltage may results in charge flow through not transitioning input pins. An example is given within the above discussed NOR3 testcase. At 100 ns (confer Figure 39) a falling transi-tion is applied to input in2. Consequently node_5 and node_8 are connected to VDD and the voltage rises. Hence the gate-drain and the gate-source capacitances of T4 are charged.
The exact fanin capacitance for delay determination and power calculation is hard to obtain.
The reason is, that the fanin capacitance is typically considered as part of the fanout capaci-tance of a driving gate. This has the following implication for a correct modelling of fanout capacitances:
• The correct consideration of all consecutive gates’ fanin capacitances as part of a fanout capacitance requires the knowledge of all node voltages (internal and external) of the driven gates,
• the fanin capacitance’s contribution to a fanout capacitance cannot be determined a priori, as the node voltages of consecutive gate’s are not constant and consequently the fanout capaci-tance needs to be calculated on the fly.
Even if a simulator allows the evaluation of signals in consecutive gates, the consideration of these signals requires a lot of effort and would undoubtedly significantly slow down the simu-lation.
In conclusion it has to be kept in mind, that the fanin contribution to a gate’s fanout capaci-tance may vary significantly (up to approximately 38% for the analysed example, if the maxi-mum fanin capacitance is characterized). From the power consumption’s point of view, charges through an input pin may even be caused by transitions at other input pins. Within the library characterization, which was needed for the simulator GliPS, the worst case fanin capac-itances were characterized (switching output).