The INS8900 and PACE CPUs have complete on-chip interrupt systems. Six separate levels of interrupts are provided: one internal and five external interrupt request inputs. including a non-maskable input. Priority logic is provided on the CPU. and all interrupts are vectored. thus eliminating any polling requirements. Because of the various ways in which interrupts can be initiated. and also because of a few problems that exist in the PACE in-terrupt system. we will divide our description of the system into three parts:
1) Low priority external interrupts 2) Internal (Stack) interrupts 3) Non-maskable (Level 0) interrupts
But first. let us take an overview of the INS8900 and PACE interrupt system.
IRO INT ENABLE
lEN
INTERRUPT
LEVEL 0 (TO CPU'S INTERNAL
INTERRUPT CONTROL CIRCUIT)
" REQUEST .-. (lRO) NHALT
J ""
STACK FULL OR
EMPTY INT REQ
,
(INTERNAL TO PACE)
s
R IR1 t-Hf-i'"" ~
IE1 4
~
NIR2
)-[>0-
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INTERRUPTIR2 PRIORITY
. f
POINTEA...
R ENCODERADDRESS
.-
~....
~IE2 ~
....
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NIR3}[>0-
S IR3i'"" R IE3
)-£>0-NIR4 S
IR4
....
RIE4
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NIR5 SIR5 i'"" R IE5
Figure 1-14. Internal View of INS8900 and PACE Interrupt System
Figu re 1-14 depicts the interrupt log ic that is contained on the CPU. The highest priority in-·
terrupt request is the non-maskable Level 0 interrupt request, which is initiated using the NHALT control input to the CPU. The lowest priority interrupt request is NIR5.
The Stack Interrupt and each of the four lower-priority external interrupt requests can be individually enabled or disabled by setting or clearing associated bits (lE1 - IE5) in the Status and Control Flag register. Notice in Figure 1-14 that these bits are shown as provid-ing the 'R' input to a latch. The'S' input to each of these latches is the actual interrupt request line. The significance of this is rather subtle. It means that an interrupt request need not supply a continuous low level until it is acknowledged. Instead, any pulse exceeding one PACE clock re-quests, it will also clear a previously latched request that mayor may not have been serviced. If this logic is not clear to you, you shou Id study the characteristics of the RS flip-flop.
A master interrupt enable (lEN) flag is also provided in the Status and Control Flag register. lEN must be set true to allow any of the latched interrupt requests to be recognized by the CPU.
The CPU checks for interrupts at the beginning of every instruction fetch. If an interrupt request is present (and enabled!. the instruction fetch is aborted, the contents of the Program Counter are pushed onto the Stack, and the master interrupt enable (lEN) is set low. The CPU then loads the Program Counter with the address vector for your interrupt service routine and executes the in-struction contained at that address. (We'll describe the address vectors in the next paragraph.)
INS8900 AND PACE INTERRUPT RESPONSE The interrupt request just described requires a total of 28 clock cycles from the time the interrupt is recognized by the CPU until the time when the first instruction of your interrupt service routine begins execution.
Memory locations 000216 through 000816 are used as pointer locations or address vectors.
You load each of these locations with the starting address of the interrupt service routine for each interrupt as follows:
INTERRUPT POINTER FOR Stack Interrupt
When the CPU responds to an interrupt. it loads the Program Counter with the contents of memory locations 2 through 6, depending on the specific level of interrupt that is being acknowledged. Control is thus vectored to the proper ser-vice routine. Suppose, for example, memory location 4 contains the value 2A3016. If an interrupt request occurring at pin NIR3 is acknowledged, then during the acknowledge process the contents of the Program Counter are saved on the Stack, following which the value 2A3016 is loaded into the Program Counter. Had the value 472816 been in memory location 4, then 472816 would have been loaded into the Program Counter instead of 2A3016. Thus. whatever memo-ry address is stored in the memomemo-ry location associated with the interrupt being acknowledged. this address will be loaded into the Program Counter, becoming the starting address for the specific interrupt service routine to be ex-ecuted.
As part of the interrupt response we've just described. the CPU sends out a low-going pulse on the CONTIN line. Refer back to Figure 1-10 and associated text for a description of the ACK INT pulse. The last instruction executed by your interrupt service routine must be a Return-from-Interrupt (RT!) instruction. This instruction sets lEN high to re-enable interrupts. then pulls the top of the Stack into the Program Counter. This returns program control to the point where it was interrupted. The RTI instruction does not clear the internal Interrupt Request latch; therefore your interrupt service routine must reset the latch (using a Pulse Flag
instruc-INS8900 been cleared. it can then be re-enabled for subsequent interrupt requests.
The interrupt sequence does not save the contents of any registers except the Program Counter. If the program that was interrupted requires that the contents of CPU registers be saved and then restored. your interrupt service routine must perform these operations.
SAVING The CPU's response to a Stack interrupt is as described for external interrupts. However. the
inter-rupt request is generated internally by the CPU chip; it can be caused either by a Stack Full or a Stack Empty condition. Remember that the 10-word Stack is part of the CPU chip. It consists of an
internal RAM and a pointer that can address Stack words 0 through 9. A Stack Empty interrupt re- INS8900 AND quest is generated whenever the pointer is at 0 and a Pull instruction is executed. A Stack Full in- PACE STACK terrupt request occurs when the pointer is at 7 (eight entries on the Stack) and a Push instruction INTERRUPTS is executed to fill the ninth word. The tenth word of the Stack will then be used as part of the
in-terrupt response to store the Program Counter contents. Unless you intend to extend the Stack out
into main memory. your application program will not require a Stack Empty or Full interrupt. These interrupts become error conditions and can be avoided by careful programming.
If your program is treating the Stack Empty and Stack Fu II interrupts as error conditions. then you can disable Stack in-terrupts. in which case the full ten words of the Stack are available for nested interrupts and subroutines. Of course.
this means that a Stack Full or Empty condition. should it occur. will become an undetected error. with unpredictable consequences.
When using PACE. but not the INS8900. there is an additional reason for not using the Stack in-terrupt capability unless you really need it. PACE has an internal circuit problem that can cause improper interrupt response. If a Stack interrupt request occurs at the same time as an NIR3 or NIR5 interrupt request, the Stack interrupt address vector will be incorrectly accessed from location 0 instead of location 2. The solution recommended in PACE literature is to load
PACE STACK INTERRUPT PROBLEMS both of these locations with the Stack interrupt vector. This apparently straightforward solution is complicated by the fact that location 0 also happens to be the initialization address; whenever the CPU is initialized. the first instruction ex-ecuted is the one that is contained in location O. Thus. the word in location 0 must serve a dual purpose:
1) It serves as an instruction whenever the CPU is initialized.
2) It serves as an address vector if a Stack interrupt occurs at the same time as NIR3 or NIR4.
Here's an example. The object code for a Copy Flags to Register (CFR) instruction is 040016. So. if locations 0 and 2 both contain a value of 040016 the problem is solved. Your Stack interrupt service routine would have to begin at memory address 040016. but you would be correctly vectored to that address regardless of whether or not the inter-rupt error we've just described occurs. On initialization. the first instruction executed would be the CFR instruction: this is not a very useful initialization instruction. but at least no damage is done.
For a fuller discussion of this interrupt problem and the solution. refer to PACE literature. Also keep in mind that the problem has been fixed in the INS8900.
The non-maskable (Level 0) interrupt cannot be disabled and differs from the other interrupt levels both in the way it is initiated and in the way the CPU responds to it.
The Level 0 interrupt request is initiated using the NHAL T control input signal in com-bination with the CONTIN input line. Figure 1-15 shows the timing relationships bet-ween NHAL T and CONTIN that are required to initiate the non-maskable interrupt. If you compare this figure with Figure 1-10. you will notice that the Level 0 interrupt request and line. The only difference between the two operations is towards the end of the timing sequence. For a Processor Stall.
NHAL T is allowed to return high whi.le CONTIN is still high; for a Level 0 interrupt. the CONTIN line must be driven low by external logic before the NHAL T line is allowed to go high. This critical timing sequence is the only way that the CPU has to differentiate between a Processor Stall and a Level 0 interrupt. Notice that this Level 0 interrupt timing sequence never requires external logic to drive CONTIN high. Therefore. if you're using the CONTIN line for any of its other multi-ple functions (including the ACK INT output pulse) you can merely tie CONTIN to ground and Use NHALT to initiate the Level 0 interrupt.
The response of the CPU to the Level 0 interrupt is subtly different from its response to other interrupts. These subtle differences are related to the slightly different purpose of a non-maskable interrupt versus a normal program interrupt request. A non-non-maskable interrupt is typically used only when there is a catastrophic error or failure (such as loss of power) or to imple-ment a control panel for program developimple-ment or debug purposes. Both of these uses require that an asynchronous. unplanned program termination have a minimum effect upon system status;