The primary memory reference instructions have typical minicomputer addressing modes. These instructions will also be used as I/O instructions. since external devices are identified via selected memory addresses . .... _ _ _ _ _ '"
In Table 1-1 . "direct addressing options" means the instruction can reference memory using any of the direct or direct indexed addressing options described earlier.
"Indirect addressing options" similarly specifies any of the indirect addressing options described earlier.
Both Branch and Skip instructions are provided. and each differs significantly from the philoso-phies described in Volume 1, Chapter 6.
INS8900 AND PACE DIRECT ADDRESSING OPTIONS
There are 16 conditions that can cause a Branch, as shown in Table 1-3 . Notice that three of the conditions are deter-mined by external inputs JC 13. 14. and 15. If a Branch-on-Condition is true. then the displacement which is added to the Program Counter is an 8-bit signed binary number as described in Volume 1. Chapter 6.
There are three varieties of Skip-on-Condition instructions. SKNE. SKG and SKAZ compare the contents of an Ac-cumulator to a memory location which is addressed using direct or direct indexed addressing. Based on the results of the comparison. the instruction following the Skip mayor may not be executed. These three instructions are therefore combined Skip and Memory Reference instructions.
ISZ and DSZ identify a memory location using direct or direct indexed addressing; the contents of the addressed memory location are incremented (ISZ) or decremented (for DSZ); if after the increment or decrement operation the memory location contains a 0 value. then the Skip is performed.
The AISZ instruction adds an 8-bit. signed binary number to the contents of an Accumulator; if the result is 0, a Skip is performed.
These Skip instructions will be very familiar to minicomputer programmers. and on most microcomputers are equivalent to a secondary Memory Reference or Immediate Operate instruction. followed by a Branch-on-Condition in-struction.
v
LEVEL 0 INTERRUPT REQUEST NOTE: If the Level 0 Interrupt request has not already been reset to a logic '1' level before lACK goes to a logic T, thenlACK should be used to reset the request signal.
'/27476 FFl 1 0 S - - - - 0 I
7404 NAOS
Q .... - - - -...
8094
lK
-
-CLR 0
'/27476 '/.74L74
FF2 FF3
CP Q
CP Q
K
CLR SET
-- 'V'/V-O
lK +5
CLR 0 '/274L74
FF4 lACK (normally '0')
Q
74L08
ODS·
INIT·
Figure 1-16. Circuit to Prevent Conflicts Between PACE Level 0 Interrupts and Lower Priority Interrupts
1-25
NHALT
PACE
CONTIN
The following symbols are used in Table 1-1 : ACO Accumulator 0
C Carry status
CC 4-bit Condition Code described in Table 15-3 D Any Destination register
DATA8 8-bit binary data unit
DISP(X) Direct or indexed addressing operands as explained in the text.
@DISP(X) Indirect addressing operands as explained in the text.
EA The effective address generated by the specified operands.
f 4-bit quantity selecting a bit in the Flag Word.
FW Flag Word described in the text.
lEN Interrupt Enable status
I A 1-bit unit determining whether LINK is included in the shift/rotate.
L Link status
n Seven bits determining how many single bit shift/rotates are performed.
o
Overflow status PC Program CounterAny register of the Accumu lator: ACO. AC 1. AC2 or AC3 S Any Source register
ST Top word of on-chip Stack.
x < y.z > Bits y through z of the quantity x. For example. r< 7.0> is the low-order byte of the specified register.
[ ] Contents of location enclosed within brackets. If a register designation is enclosed within the brackets.
then the designated register's contents are specified. If a memory address is enclosed within the brackets.
then the contents of the addressed memory location are specified.
£[ ]] Implied memory addressing; the contents of the memory location designated by the contents of a register.
A Logical AND
V Logical OR
.:v-
Logical Exclusive-ORData is transferred in the direction of the arrow.
Data is exchanged between the two locations designated on either side of the arrow.
Under the heading of STATUSES in Table 1-1 . an X indicates statuses which are modified in the course of the instruc-tion's execution. If there is no X. it means that the status maintains the value it had before the instruction was ex-ecuted.
Table 1-1. INS8900 and PACE Instruction Set Summary
STATUSES
TYPE MNEMONIC OPERAND(SI BYTES OPERA nON PERFORMED
c 0 L
LD r.DISP(X) 2 [rl-[EA]
w Load any Accumulator, direct addressing options.
0 LD O,@DISP(X) 2 [ACO]-[EA]
z w Load Primary Accumulator, indirect addressing options.
> II:
II: W 0 ST r,DISP(X) 2 [EA]-[rl
c( ~
--::; ~
;;
Store any Accumulator. direct addressing options.ii: > Z
Q. II: c( ST O,@IDISP(X) 2 [ EA]-[ACO]
0 Store Primary Accumulator, indirect addressing options.
:!: W LSEX O,DISP(X) 2 [ACO]-[ EA](sign extended)
:!: Load a signed byte into Primary Accumulator; extend sign bit into high order byte. Direct
addressing options.
N
-..JADD r.DISP(X) 2 X X [r]-[r]+[EA]
w _ Add to any Accumulator. direct addressing options.
o z W I- DEC A O,DISP(X) 2 X X [ACO]-[ ACO]-:-l EA]-.- [C)
> W c(
Add decimal with Carry to any Accumulator, direct addressing options.
II: II: II:
c( ~ ~ SUBB O,DISP(X) 2 X X [ACO]-[ACO] - [EA].+lC]
o W 0
Z II: > Subtract from Primary Accumulator with borrow, direct addressing options.
o > II:
o II: 0 AND O,DISP(X) 2 [ACO]-[ACO]/\ [EA]
~ ~ !
AND with Primary Accumulator, direct addressing options.w:!:
:!:- OR O,DISP(X) 2 [ACO]-[ ACO] V [EA]
OR with Primary Accumulator, direct addressing options.
_LI r,DATA8 2 [r< 7,0>]- DATA8 (sign extended)
W Load immediate into any Accumulator. DATA8 is an 8-bit signed binary value. The sign bit
I-e( is propagated through 8 high order bits.
C JMP DISP(X) 2 [PC]-EA
W
Jump by loading the effective difect address into the Program Counter.
:!: ~ JMP @DISP(X) 2 [PC]-EA
Jump by loading the effective indirect address into the Program Counter.
... - _ . _ - - - - - - - - - - - - - _ . _ - -
-Table 1-1. INS8900 and PACE Instruction Set Summary (Continued)
STATUSES
TYPE MNEMONIC OPERAND(SI BYTES OPERATION PERFORMED
C 0 L
JSR DISP(XI 2 [STl-[ PCl
I&IQ [PC]-EA
1-1&1 Jump to subroutine direct. As JMP direct. but push old Program Counter contents onto
~i
Stack.~~
JSR @OISP(X) 2 [STJ-[ PC]~O [PC]-EA
- g
Jump to subroutine indirect. As JMP indirect. but push old Program Counter contents onto Stack.
1&1 CAl r.DATAB 2 [rl-[ r] +DATAB (sign extended)
1-1&1
c( ... Complement contents of any register. then add immediate data.
co ~
Q~ 1&11&1
~o. ~O
Zz SOC CC.DISP 2 If CC true: then [PCJ- EA
0 0 Branch on CC true. as defined in Table 14-3.
iSE
ZQ c(Z a:0 II:IU1&1
SKNE r.DISP(X) 2 If [rl " [EA]: then [PC]-[ PC] + 1
U Z
Skip if any Accumulator not equal.
1&1
a:o.i=
SKG O.DISP(X) 2 If [ACO] > [EA]: then [PC]-[PC]+ 1
~i2~
~U) ... Skip if Primary Accumulator greater.
>01&1 SKAZ O.DISP(X) 2 If ([ ACO] /\ (EA]) = 0: then [PC]-[ PC] + 1
a:ZI&I
Oc(5!l Skip if AND with Primary Accumulator is zero.
~ 1&1
~
~
...,
Add immediate to any Accumulator. Skip if zero. DATA8 is an 8·bit signed binary immedi-ate data value.
[D]-[S]
Move contents of any Accumulator (S) to any Accumulator (D).
[D]--[S]
Exchange contents of any Accumulators.
[D]-[S]+[D]
Binary add any Accumulator to any Accumulator.
[D]-[S1+[D]+[C]
Binary add with Carry any Accumulator to any Accumulator.
[D]-[S] 1\ [D)
AND any Accumulator with any Accumulator.
[D]-[S] ¥[D]
Exclusive-OR any Accumulator with any Accumulator.
Shift any Accumulator left n bits. Simple if 1 = 0; through Link if 1 = 1.
Shift any Accumulator left n bits. Simple if 1 = O. through Link if , = 1.
As SHL. but rotate.
As SHR. but rotate.
Table 1-1. INS8900 and PACE Instruction Set Summary (Continued)
STATUSES
TYPE MNEMONIC OPERAND(S) BYTES OPERATION PERFORMED
C 0 L
PUSH r 2 [ST]-[r]
Push any Accumulator contents onto Stack.
PUSHF 2 [ST1-[FW]
Push flags onto Stack.
PULL r 2 [r1-[ST]
~ Pull top of Stack into any Accumulator.
u ~ PULLF 2 X X X [FW]-[ST1
en Pull top of Stack into flags.
XCHRS r 2 [ST1--[r]
Exchange contents of any Accumulator with top of Stack.
RTS DISP 2 [PC]-[ ST1 + DISP
....
iN
oReturn from subroutine. Move sum of DISP and top of Stack to PC. DISP is an a-bit signed binary number.
I- RTI DISP 2 [PC]-[ ST]+ DISP
~
:I [IEN]-1
II: II:
Return from interrupt. Like RTS. but enable interrupts.
w
I-~
CFR r 2 [r1-[FWI
Copy flags to any Accumulator.
CRF r 2 X X X [FW]-Er1
en Move any Accumulator contents to flags.
:::I
I-c( SFLG f 2 [FW<f>1-1
I- Set flag I to 1. (f= 0 to 15).
en
PFLG f 2 [ FW < f>]- 1 for lour clock periods
Pulse flag f (invert flag status for four clock periods). (f = 0 to 15).
HALT 2 Halt
The following symbols are used in Table 1-2:
aa Two bits choosing the destination register.
bb Two bits choosing the Index register Eight bits of immediate data A "don't care" bit
A "don't care" byte
Table 1-2. INS8900 and PACE Instruction Set Object Codes
MACHINE CYCLES INSTRUCTION OBJECT CODE BYTES
TOTAL INTERNAL INPUT OUTPUT
ADD r,DISP(X) 1110aabb 2 4 2 2
Table 1-2. INS8900 and PACE Instruction Set Object Codes (Continued)
MACHINE CYCLES INSTRUCTION OBJECT CODE BYTES
TOTAL INTERNAL INf:»UT OUTPUT
PFLG f oollffff 2 6 5 1
Oxxxxxxx
PULL r 01100laa 2 4 3 1
XX
PULLF 000looxx 2 4 3 1
XX
PUSH r 011000aa 2 4 3 1
XX
PUSHF 0000llxx 2 4 3 1
XX
RADC S,D 0011101aa 2 4 3 1
eexxxxxx
RADD S,D 011010aa 2 4 3 1
eexxxxxx
RAND S,D 010101aa 2 4 3 1
eexxxxxx
RCPY S,D 010111aa 2 4 3 1
eexxxxxx
ROL r,n,1 ool000aa 2 5+3n 4+3n 1
nnnnnnni
ROR r,n,1 00loolaa 2 5 + 3n 4+3n 1
nnnnnnni
RTI 011111xx 2 6 5 1
pp
RTS 100000xx 2 5 4 1
PP
RXCH S,D 011011aa 2 6 5 1
eexxxxxx
RXOR S,D 010110aa 2 4 3 1
eexxxxxx
SFLG f oollffff 2 5 4 1
1xxxxxxx
SHL r,n,1 oo1010aa 2 5+ 3n 4+3n 1
nnnnnnni
SHR r,n,1 oo1011aa 2 5+3n 4+3n 1
nnnnnnni
SKAZ O,DISP(X) 101110bb 2 5/6 3/4 2
PP
SKG O,DISP(X) 100lllbb 2 7/8 5/6 2
pp "
SKNE r,DISP(X) 1111aabb 2 5/6 3/4 2
PP
ST r,DISP(X) 1101aabb 2 4 2 1 1
PP
ST O,@\DISP (X) 101100bb 2 4 1 2 1
pp
SUBB O,DISP(X) 1ool00bb 2 4 2 2
PP
XCHRS r 000lllaa 2 6 5 1
XX
·AII instructions may take additional cycles if Extend Read and Extend Write are implemented.
Table 1-3. Branch Conditions for INS8900 and PACE BOC Instruction
Condition Mnemonic Condition
Code (CC)