DEMULTIPLEXING THEINS8900

be included in an INS8900system.

Let us see how 8080A support devices might be used with the INS8900 CPU. First, we'll take an overview of the general CPU-to-device interface that all the 8080A family of devices expect.

All of the 8080A family devices require that address information (or enabling/select signals derived from the ad-dress lines) be valid during the data transfer (read/write) portion of an input/output cycle. Recall that the INS8900 data lines are multiplexed: at the beginning of an input/output cycle. the data lines are used to output address informa-tion; the address information is then removed and the data lines are used for the actual input or output of data during the latter portion of the I/O cycle.

Thus, the first thing we must do to interface the INS8900 to an 8080A family device is to demultiplex the INS8900 address/data lines. There are several different approaches that we can use to accomplish the required demultiplexing.

The most obvious way is to use D-type flip-flops or data registers with the INS8900

DEMULTIPLEXING THEINS8900 ADDRESS/DATA LINES

NADS signal as the clock pulse. Here are some of the standard 7400 family devices that might be used:

·7475 Double 2-Bit Gated Latches with Q and Q Outputs

·7477 Double 2-Bit Gated Latches with Q Output Only

• 74100 Double 4-Bit Gated Latches

·74166 Dual 4-Bit Gated Latches with Clear

·74174 Hex D-Type Flip-Flops with Common Clock and Clear

·74175 Quad D-Type Flip-Flops with Common Clock and Clear

Some of these devices require that the NADS signal be inverted to provide the necessary clocking Signal. Remember.

though. that PACE address information is valid during both the leading edge (high-to-Iow transition) and trailing edge (Iow-to-high transition) of NADS; this generally simplifies the demultiplexing operation.

In many systems you will not need to latch all16 bits of address information since it would be an unusual applica-tion that required all of the 64K of address space that this provides. There will usually be some tradeoff between system address requirements (how many system devices require a latched Address Bus) and the type and amount of address decoding required. When a fully latched Address Bus is provided. then simpler nonlatched address decoders can be used. In fact. often address bits can then be used directly as device select signals. or simple AND/OR gate combina-tions can perform the decoding.

The alternative method of demultiplexing the address/data lines is to use address decoding devices that are clocked by the NADS signal and provide latched outputs. These latched outputs can then be used as the device/chip select Signals during I/O cycles.

Many systems will use some combination of a fully latched Address Bus and simple or latched address decoders. In the discussions that follow, we will not generally describe in detail the method used to obtain the required addressing or select/enabling signals, since the method used is so dependent on the particular system that you are designing.

Once the INS8900 address/data lines have been demultiplexed, the only major con- INS8900 CONTROL siderations we are left with are to ensure that the input/output control signals are of SIGNAL POLARITY the proper polarity, and to verify that there are no timing problems. We will see that CONSIDERATIONS generally the INS8900 I/O control signals must be inverted to operate with the 8080A

family of devices. although the 8212 offers us a choice of using the IDS and ODS signals. in either their original or in-verted form.

Now we will provide a few specific examples of how devices from the 8080A family can be used with the INS8900 CPU.

In our first example the 8212 I/O Port is used as a simple input port by the INS8900 CPU.

The interconnections required are shown in the following figure:

THE 8212 USED AS A SIMPLE INPUT PORT IN AN INS8900 SYSTEM Data to

INS8900 CPU (System Bus)

Derived from - - - -. .

a

Address Lines

1 0 S - - - -...

(from INS89(0)

NADS (from INS89(0)

DOO

D07

Ds1

DS2

STB

cur

NINIT---~

DIO

Data from external logic DI7

8212

Tie MD to Ground. Now STB clocks latches and DSi. DS2 enable buffers.

MD

-

-Here, the INS8900 Address Strobe signal (NADS) is inverted and used as the STB input to the 8212. Since MD is tied to ground, the STB signal clocks the data into the 8212: this will occur every time the INS8900 performs an input/output cycle, but the latched data will only be placed on the System Bus when the 8212 is selected.

We accomplish device selection by applying a negative-true decoded address signal to the OS 1 input and then using the INS8900 IDS strobe signal as the DS2 input. Now, whenever the proper address is decoded, the IDS signal will cause the data that was previously latched by NADS to be placed on the System Bus for input to the INS8900. The timing would look like this:

NADS

STB

DIO - DI7

OS2 (IDS)

000- 007

r----,

Latched data output onto System Bus

1-39

Notice that the data from external logic will be latched whenever NADS occurs. The actual selection of the 8212 and input of the latched data to the INS8900 might not occur for quite some time. Frequently, this arrangement will be completely acceptable. If not. then an input-with-handshaking arrangement. which we will describe next. might pro-vide a better solution.

Before we proceed to our next example. let us make one more general comment about interfacing devices to the INS8900 CPU.

The INS8900 is a 16-bit microcomputer: it can transfer 16 bits of parallel data in a single input or output cycle.

All of the other devices that we will be discussing are 8-bit devices. Frequently. you may not need the full width of the 16-bit Data Bus when transferring data between the CPU and external logic. In these cases, you can simply connect the data lines to/from the support device to the less significant data lines (DO - 07) of the INS8900 System Bus, as we have shown in our first example. Masking of the unused, more significant data bits would then be handled under program control.

When you are going to utilize the full 16 bits of the Data Bus. you merely connect two 8-bit devices in parallel.

as described in more detail for the CP1600 in Chapter 2. One device would be connected as we've already de-scribed; the data lines of the other device would then be connected to the more significant bits (08 - 015) of the System Bus. All other connections to the two devices (device select signals. strobe signals. etc.) would be identical.

In this example. we will use the 8212 interrupt request signal INT to establish an input port with handshaking. The connection diagram is very similar to our first exam.ple:

THE 8212 USED

xternal logic strobes ata into latches NADS signal to clock data into the latches, we will require external logic to input the STB signal when it has data ready. When the data has been latched. the 8212 will output the INT signal. which will be used as the in-put to one of the INS8900 CPU interrupt request lines (NIR2 - NIR5) or Jump Condition inin-puts (JC13 - JC15).

The CPU,will then execute a service routine program that will include an instruction to read the data from the input port. This instruction will send out the input port's address, thus generating the DS 1 signal. and then gate the latched

data onto the System Bus when the IDS signal is generated. When the latched data is read out of the 8212. the INT sig-nal returns high to complete the transaction. This sequence is summarized by the following timing diagram

010 - 017

STB

----'

OS2 (lOSl

DOO - 007

Data latched by external logic

.. --- .. ^{--- ..}

^~~

^....

^,

^{... -- ....}

^~~--

..

^~

...

-Interrupt request or Jump condition input to INS8900 CPU

onto System Bus

Using the 8212 as an output port in an INS8900 system requires a simple reversal of the connections we have described in the two preceding examples. and we will now use the ODS (Output Data Strobe) signal from the INS8900 instead of the IDS signal.

010 000

Data from

Data to external

INS8900 CPU logic

(System Busl

017 007

THE 8212 USED AS AN OUTPUT PORT IN AN INS8900 SYSTEM

8212

DsT

Select signals generated

ODS by external logic

(from INS8900) STB OS2

Select Signal MO

M

To external logic

derived from

• •

Address Lines

- _-

to INS8900

• ^{: •}

~ ______ J interrupt lines

or JC inputs

When the output port's address is sent out and decoded from the Address Bus, one input to the AND gate is enabled.

The ODS signal then goes high to generate the STB signal and latch the contents of the system Data Bus into the 8212.

This will cause the INT signal to go low and inform external logic that data has been loaded into the output port. The external logic will then generate the DS1 and DS2 signals to gate the data out of the latches. When the data has been gated out. the

TNT

signal will return high. This low-to-high transition could be used as an interrupt request or jump con-dition input to an INS8900 to enable output of new data. Notice that if we continuously enable the 8212 outputs by tying CST to ground and DS2 to +5V, then whenever the INS8900 loads a new data word into the latch, it will be immediately output to external logic. This approach may be more advantageous in some applications.

Although the 8255 Programmable Peripheral Interface (PPl) is a more complicated device than the 8212, interfacing the 8255 to an INS8900 CPU is no more complicated (from a hardware point of view) than the INS8900-to-8212 interfaces we've described.

This is due to the programmability of the 8255; mode control is performed by your pro-gram instead of by hardwired signals. Let us look at an example to illustrate this point:

To/From INS8900 CPU (System Bus)

Decoded Select - - - - -... .,..;;.11 signal derived

from Address Bus From latched {

Address Bus

---1

From INS8900

CPU

l

^{ODS iDS}

NINIT

DO

07

CS

8255 AO

A1

AD

WR

RESET

8255 PPI DEVICES USED IN AN INS8900 SYSTEM

To/From Extemal Logic

The CS signal selects the 8255 and this signal would typically be the output of an address decoder. The AO and A 1 inputs select one of the three I/O ports (A, B or C) or the 8255 Control registers. The RD and WR control sig-nals are obtained by simply inverting the IDS and ODS sigsig-nals from PACE. A generalized timing diagram for in-put/output operations would look like this:

NADS

~

CS·AO·A1

_ _ _ _ _ .. Select Device and Port Select

IDS (ODS) _ _ _ _ _ _ _ _ _ _

~

m~ ~ ?

Data transferred

If two· 8255s are used in parallel to provide 16-bit I/O ports. there is one special con-sideration beyond the general rules that we discussed earlier. Recall that mode control of the 8255 is accomplished by writing data into one 8-bit Control register within the device. When wired in parallel. one 8255 would be connected to bits 0 - 7 of the system Data Bus. and the other 8255 would be connected to bits 8 - 15. Therefore. when we send out a 16-bit control word from the INS8900 CPU to establish the desired mode of operation. the upper and lower bytes of the word must be identical.

From a hardware point of view. interfacing either of these devices to an INS8900 CPU is no different than interfacing an 8255 PPI to the INS8900. All we need to do is invert the IDS and ODS signals from the CPU to obtain RD and WR (or lOR and lOW) signals. and provide chip select and latched address bits for input to the devices. All other interfacing and usage considerations are software functions and are described in Chapter 4. We will not describe them here since those portions of the device descriptions apply regardless of the CPUbeilig used.

We will conclude our discussion of the use of 8080A devices in INS8900 systems by comparing INS8900 System Bus signals with those of 8080A systems. This comparison will be a useful guide for interfacing any 8080A device to an INS8900 system. Table 1-5 is a summary of INS8900 System Bus signals and the corresponding signals availa-ble in 8080A systems. Two separate columns are provided for 8080A signals: the first

Since we have already discussed these signals in preceding paragraphs, we won't perform an item-by-item analysis of the table. Nonetheless, there are a few signals in this table that do need additional explanation.

We have included the INS8900 BPS signal in the I/O Control Signal group although it is not the type of signal you would normally classify within this group. However. you will recall that when the BPS input is high. the INS8900 operates in a Base-Page-Split mode; base page then consists of the top 128 words of memory and the bottom 128 words of memory. In our earlier discussion of the BPS Signal. we described how this mode can be used to simplify ad-dressing of I/O devices. If you refer back to that discussion, you will see that by doing a little address decoding we can come up with a signal that will tell us when the INS8900 is addressing an I/O device (as opposed to memory).

Let us call this decoded signal '1/0 Device' (100). Now, we can combine this decoded signal with IDS and ODS as shown below to generate signals equivalent to the 8080A liaR and

tlow

signals.

IDS ---~--""

~---VOR

1/00 - - - _

K>---I/OW

OOS---~---L

__

^~

And if we invert the 1/00 signal we can generate the 8080A MEMR.and MEMW signals.

1 0 S - . . . ; . . . . - - - , . - - " " " "

One other portion of Table 1-5 requires some explanation. Notice that we have not drawn a line to separate the I/O control signals from the DMA-Related Signals. We've done this intentionally because there is some overlap-ping of functions with some of these signal,. For example, the INS8900 EXTEND 'signal can be used either to extend I/O cycles or to suspend I/O to allow DMA operations. We've also compared the INS8900 NHAl T output signal to the 8080A WAIT signal. This comparison is valid if limited to the CPU Halt state initiated in either system by a Halt instruc-tion. However, in 8080A systems the WAIT signal is also an acknowledgement to the READY or RDYIN input signals.

There is no comparable EXTEND acknowledgement signal in PACE systems.

The 6800 family includes many devices that might be useful in INS8900 systems, Unfor-tunately. all of these devices have one common requirement which effectively makes them incompatible for use in an INS8900 system. That requirement is enabling input signal E which should more accurately be described as a synchronizing signal. In 6800 systems. E is usually

INS8900 8080A 8080A SYSTEM

SYSTEM BUS SYSTEM CPU (CPU. 8228. 8224)

SIGNALS SIGNALS SIGNALS

Bidirectional 000 - 015 00- 07 DBO - DB7

Data Bus (16 Bits) (8 Bits) (8 Bits)

Address Bus 000 - 015 AO-A15 AO-A15

Address information must be demultiplexed from Data Bus

Initialize NINIT RESET RESIN

Jump Condition JC13-JC15

-

-Inputs

Control Flag _Outputs F11 - F14

-

Im Dokument 16-Bit Microprocessor (Seite 52-58)