CP1600 INSTRUCTION TIMING AND EXECUTION
CP1600 MEMORY ACCESS TIMING
Tl, T21 T31
T4
I I I
MEMORY READ
NACT DTB
MC2 MC3
I I I I I I
I I I I I I Tli T2, T3, T4 Tl'T2, T3 ,T4
, I I ' "
Data address out Data in
Figure 2-5. CP 1600 Timing for Memory Read I nstruction with Implied Memory Addressing
CP1600 INSTRUCTION TIMING AND EXECUTION
CP1600 instructions are executed as a sequence of machine cycles. Each machine cycle has four clock periods, as illustrated in Figure 2-3. Machine cycles are identified by their cycle number and by the levels of the BC1. BC2.
and BDIR signals. Each of the eight level combinations is given a name. taken from Table 2-1. This name becomes the name of the machine cycle. Thus in Figure 2-4. and in subsequent instruction timing illustrations. each machine cy-cle is identified by a signal name from Table 2-1.
Figure 2-3 shows general case timing for data output or input on the Data/Address Bus. In between data input or out-put operations the bus is floated.
CP1600 MEMORY ACCESS TIMING
Figure 2-4 illustrates instruction fetch timing for a CP1600 instruction's execution. Three machine cycles are re-quired. During the first mac.hine cycle an address is output. Nothing happens during the second machine cycle: it is a
"time spacing" machine cycle that routinely separates two CP1600 Bus access machine cycles. The object code for the accessed instruction is returned during the third machine cycle.
Figure 2-5 illustrates timing for the simplest memory read instruction's execution. In this .case the data memory address is taken from one of the CPU registers. There is no difference between timing for the three machine cycles of an instruction fetch or a data memory read. As illustrated in Figure 2-5. a simple memory read instruction's execution consists of two three-machine cycle memory read operations. separated by a spacing no operation machine cycle.
BAR MCl I I ,
INSTRUCTION FETCH NACT
MC2
DTB
MC3 NACT BAR
MCl
MEMORY WRITE NACT
MC2
DW MC3
DWS MC4
I I I I , I I 1 I I I . I I I I I I I I I
Tl :T2:T3:T4 I . , I I I " I I I I , I I I , I I I I
Tli T2,T3.T4 Tl, T2, T3. T4 Tl, T2, T3,T4 Tl,T21 T31 T4 Tl, T2, T3, T4 Tl, T2. T3, T4 Tl, T21 T3.T4
, , . I I I I I ' I • I I ' I I I
I I I
Instruction address out
Instruction object code in
Data address out Data out
Figure 2-6. CP1600 Timing for Memory Write Instruction with Implied Memory Addressing
Figure 2-6 illustrates timing for a simple CP1600 memory write instruction execution. Data is output for two machine cycles. giving external logic ample time to respond to the data output. External logic uses the DWS machine cycle as a write strobe.
Any memory reference instruction that specifies direct memory addressing will require one three-clock-period machine cycle to fetch each word of the instruction object code: an NACT clock period will separate each machine cycle. After the first instruction fetch machine cycle. an ADAR-NACT clock period combination will be inserted in the second (and third. if present) instruction fetch machine cycle. During an ADAR clock period. BC1 is high. while BC2 and BDIR are low. No other control signals are active. Thus. for a two-word memory read or memory write instruction that specifies direct addressing, the following clock periods and machine cycles will be required for instruction ex-ecution:
Direct Addressing Memory Read Machine Cycles
Direct Addressing Memory Write Machine Cycle
BAR } Fetch first instruction { BAR
NACT "~---object code word ---t.~ NACT
DTB DTB
NACT .. 4.---Spacing machine c y c l e - - - -... ~NACT
~~~~}
.. '4.----Fetch secondinstruction---t.~{ ~~~~
NACT object code word NACT
DTB DTB
NACT ... - - - Spacing machine cycle---.~ NACT
BAR } Memory read Memory write { BAR
NACT ... ---machine cycle machine cycle---__ .~ NACT
DTB DW
DWS 2-11
BAR NACT NACT
<1>2
BC1
---+---BC2
BOIR
BOROY
Figure 2-7. CP1600 Wait State Timing THE CP1600 WAIT STATE
The CP1600 has a Wait state equivalent to those described for other microcomputers in this book. External logic that requires more time to respond to an access must input BDRDY low before the end of the BAR machine cycle. during which an address is output and the device is selected. Timing is illustrated in Figure 2-7.
If you examine Figures 2-4, 2-5 and 2-6. you will see that an address is output during a BAR machine cycle to initi-ate any external device access. The BAR machine cycle is always followed by an NACT machine cycle; in the middle of T1 during this NACT machine cycle, the CP1600 samples BDRDY. If ~ is low. then a sequence of NACT machine cycles occurs. In the middle of T4 for every NACT machine cycle, the CP1600 samples BDRDY again. Upon detecting BDRDY high, the CP1600 resumes instruction execution with a DTB machine cycle.
A Wait state must last for less than 40 microseconds, since the CP1600 is a dynamic device.
THE CP1600 HALT STATE
The CP1600 has a Halt state which may follow execution of the Halt instruction, or may be initiated by external logic.
When the Halt instruction is executed. then. following the instruction fetch machine cycle, the HALT signal is output high and a sequence of NACT machine cycles is executed.
External logic initiates a Halt state by making the STPST input undergo a high-to-Iow transition. Following execution of the next interruptable instruction. a Halt state begins. The HALT signal is output high and a sequence of NACT machine cycles is executed.
A Halt state, whether it is initiated by execution of a Halt instruction or by a high-to-Iow transition of STPST. must be terminated by a high-to-Iow transition of STPST. This will cause the Halt state to end at the conclusion of the next NACT machine cycle. Timing for a Halt state which is initiated and terminated by STPST may be illustrated as follows:
STPST{L-_ _ l ~
HALT
~~---~~---Next interruptable
~
\ . y )1
instruction's / \
execution HALT STATE Next NACT machine
ends here cycle ends here
The
PerF
signal as an input inhibits CP1600 Program Counter increment logic. Thus. external logic can input PCIT low - in which case the same instruction will be continuously re-executed until PC IT goes high again. However. PCIT should only change levels while the CPU has been halted. Thus. PCIT and STPST should be used together as follows:PCIT REQUEST
STPST
PCIT