The CP1600 instruction set is relatively straightforward. Addressing modes, which we have already described, are sim-ple, and instructions are typical of those we have seen and described for other microcomputers. Unusual features relat-ing to addressrelat-ing modes available with individual instructions are summarized in Table 2-2, which describes the CP1600 instruction set.
If you have never programmed a PDP-11 minicomputer, then you should pay particular attention to program-ming techniques that result from the Stack Pointer and Program Counter being accessed as general purpose registers.
A wide variety of Register Operate instructions allow you to compute data and load the result directly into Register R7, the Program Counter. In effect these become computed Jump instructions.
The ability to manipulate Register R6, the Stack Pointer, as though it were a general purpose register means that it is easy to maintain a number of different Stacks in external read/write memory.
The Jump-to-Subroutine instruction has a minicomputer flavor to it. Rather than saving the return address on the Stack, Register R7 contents are moved to General Purpose Register R4 or R5. A number of minicomputers will save a subroutine return address in a general purpose register in this fashion. The problem with this logic is that you must ex-ecute an additional instruction within the subroutine to save the return address on the Stack if you are going to use nesting subroutines. If you are passing subroutine parameters, however, this is an excellent arrangement for the Jump-to-Subroutine instruction places the address of the parameter list directly in a Data Counter with auto-increment. We have described the concept of parameter passing in Volume 1, Chapter 7.
Note that the CP 1600 instruction set lacks a logical OR.
In Tables 2-2 and 2-4, instruction length is given in terms of "words" rather than "bytes", as we have done in pre-vious chapters. Since only the lower 10 bits of the CP1600 object code are presently used, system configurations need not have the full 16-bit word size. Hence a "word" may be 10 to 16 bits wide, depending on the implementation.
The following notation is used in Table 2-2:
ADDR One word of direct address
condCondition on which a branch may be taken. Table 1-3 lists all 14 branch conditions.
DATA One word of immediate data.
DISP One word displacement. See Table 2-4 for location of sign bit.
E External branch condition.
EBCAO-3 The external branch condition address lines: EBCAO, EBCA 1, EBCA2, and EBCA3.
EBCI The external branch condition input line.
LABEL A 16-bit direct address, target of a Jump instruction. See Table 2-4 for the bit format.
PC IT The software interrupt output line.
RB General Purpose Register R4, R5, or R6.
RD One of the general purpose registers, used as a destination for operation results.
RM One of the general purpose registers used as a Data Counter, R4 or R5, if specified, is auto-incremented after the memory access. R6 is incremented after a write, and decremented before a read.
RR General Purpose Register RO, R1, R2, or R3.
RS One of the general purpose registers, used as the source of an operand.
Statuses:
S the Sign status C the Carry status Z the Zero status
o
the Overflow statusThe following symbols are used in the STATUSES column:
X the status flag is affected by the operation a blank means the status flag is not affected
°
the operation clears the status flag 1 the operation sets the flag2 the Overflow flag is affected only on 2-bit shifts or rotates
SW The Status Word. whose bits correspond to the condition of the status flags in the following way:
x<y.Z>
(.2)
3 2 1 0 .... Bit No
I s I z laic I
Status WordWhen the status word is copied into a register. it goes to the upper half of each byte:
[SW]
When the status word is loaded from a register. it comes from the upper half of the lower byte:
~11-5---8·1-7--~::::rr~-4~3---~ol ~~3~~---o~1
[RS] [SW]
Bits y through z of the Register x. For example. R7
<
15.8>
represents the upper byte of the Program CounterIndicates that the operand ".2" is optional A low pulse
[ ] Contents of location enclosed within brackets. If a register designation is enclosed within the brackets.
then the designated register's contents are specified. If a memory address is enclosed within the brackets.
then the contents of the addressed memory location are specified.
[[ ]] Implied memory addressing: the contents of the memory location designated by the contents of a register.
A Logical AND
-¥- Logical Exclusive-OR
± Addition or subtraction of a displacement. depending on the sign bit in the object code.
Data is transferred in the direction of the arrow.
Table 2-2. CP1600 Instruction Set Summary
sTAtuses
TYPE MNEMONIC OPERAND(S) WORDS S Z C 0 OPERATION PE~FORMED
MVI ADDR,RD 2 [RD]-[ADDR]
Load register from memory, using direct addressing.
O~II.I MVI@ RM,RD 1 [RD]-[[RM))
::::0(,) >~z Load register from memory, using implied addressing.
~~ffi
MVO RS,ADDR 2 [ADDR]-[RS]~Q~ Store register to memory, using direct addressing.
a::Za:: MVO@ RSJIM 1 [[RM))-[RS]
ILc(
Stbre register to memory, using implied addressing. If RS=R4, R5, R6 or R7, then RS=RM Is not supported.
ADD ADDR,RD 2 X X X X [RD]-[RD)+ [ADDR]
~
....
co
11.1 Add memory contents to register, using direct addressing.
(,) ADD@ RM,Rt) 1 X X X X [RD]-[RD]+ [[RM))
Z 11.1 Add memory contents to register, using implied addressing.
a:: 11.1 SUB ADDR,RD 2 X X X X [RD]-[RD] - [ADDR]
u. 11.1
Subtract memory tontents from registEir, using direct addressing.
a::
> SUB@ RM,RD 1 X X X X [RD]-[RD] - [[RM]]
a:: Subtract memory contents from register, using implied addressing.
0
~ CMP ADDR,RS 2 X X X X [RS] - [ADDR]
11.1
Compare memory contents with registers, u$ing direct addressing. Only the status flags are :E
Q affected.
Z CMP@
c( RM,RS 1 X X X X [RS] - [(RM))
g
Compare memory contents with register's, using implied addressing. Only the status flags areaffected.
> AND ADDR,RO 2 X X [RD]-[RD] A [AOOR]
II! AND memory contents with those of register, using direct addressing.
c(
Q AND@ RM;RD 1 X X tRD]-[RD) A [[RM))
z 0 AND memory contents with those of register, using implied addressing.
(,) w XOR ADDR,RD 2 X X [RD]-[RD]-¥- [ADDR]
en
Exclusive-OR memory contents with those of register, using direct addressing.
XOR@ RM,RD 1 X X [RD]-[ RO].y. [[ RM))
Exclusive-OR memory contents with those of register, using implied addressing.
Table 2-2. CP1600 Instruction Set Summary (Continued) STATUSES
TYPE MNEMONIC OPERAND(S) WORDS S Z C 0 OPERATION PERFORMED
w MVII DATA,RD 2 [RD]~DATA
~
0( Load immediate to specified register.
Q w MVOI RS,DATA 2 [[R7] + l1~[AS]
~ Store contents of specified register in immediate field of MVOI instruction, This is only possible if
~ program memory is reed/write memory (rather than ROM). I !
ADDI DATA,RD 2
w X X X X [RD]~[RD] + DATA
~ Add immediate to specified register.
0( a: w SUBI DATA,RD 2 X X X X [RD]~[RD] - DATA
A. Subtract immediate data froni specified register.
0
w CMPI DATA,RS 2 X X X X [RD]-DATA
~
t;-J
0( Compare immediate data with contents of specified register. Only the status flags are affected.
is ANDI DATA,RD 2 X X [RD]~[RD] A DATA
w I
~ AND immediate data with contents of specified register.
~ XORI DATA,RD 2 X X [RD]~[RDl¥DATA
CD
Exclusive-OR immediate data wit., contents of specified register.
J LABEL 3 [R7]~LABEL
Jump to given address. I
A. JR AS 1 X X [R7]~[RS]
:i! :;) ..., JSR RB,LABEL 3 [RB]~[R7l; [R7]~LABEL Jump to address contained in specified register.
Jump to given address, saving Program Counter in A4, R5, or AS.
B DISP 2 [R71~[R7] + 2±DISP
Branch relative to Program Counter contents.
z Z Bcond DISP 2 If cond is true, [A7]~[ A71 + 2±DISP
o 0 Branch relative on given condition; otherwise, execute next sequential instruction. I
~
E
BEXT DISP,E 2 EBCAO-3 ~E;Z Q
0( Z If EBCI=l, [R7]~[R7]+2±DISP
a: 0
III 0 Branch relative if external condition is true.
Table 2-2. CP1600 Instruction Set Summary (Continued) STATUSES
TYPE MNEMONIC OPERAND(S) WORDS S Z C 0 OPERATION PERFORMED
MOVR RS,RD 1 X x [RD]-[RS]
a:'" Move contents of source register to destination register.
",'"
ADDR RS,RD 1 X X X X [RD]-[RS]+ [RD]... C
Add contents of specified registers.
en a:
-'"
c,,1L SUBR RS,RD 1 X X X X [RD]-[ RD] - [RS]
"'0
lIFe Subtract contents of source register from those of destination register.
a:Z CMPR RS,RD 1 X X X X [RD]- [RS]
~C !!~ Compera registera' contents. Only the status flags ara affected.
&!o
ANDR RS,RD 1 X X [RD]-[RD] A [RS]a::I AND contents of specified registers.
XORR RS,RD 1 X X [RD]-[RD].y.[RS]
Exclu,ive-OR contents of specified registera.
II-)
N
o CLRR RD 1 0 1 [RD]-[RD] V [RD]Clear specified register.
TSTR RS 1 X X [RS]-[RS]
Test contents of specified register.
INCR RD 1 X X [RD]-[RD]+l
'"
Incremant contents of specified register.~
DECR RD 1 X X [RD]-[RD] - 1'"
Decrement contants of specified ragister.IL 0 COMR RD 1 X X [RD]-[RD]
a:
'"
Complement contents of specified ragister (ones complement)....
en NEGR RD 1 X X X X [RD]-[RD] + 1C;
'"
Nagate contents of specified register (twOI complement).a: ADCR RD 1 X X X X [RD]-[RD]+ [e)
Add Carry bit to lpecified regilter contentl.
SLL RR(.2) 1 X X
1
15+ - - 01+-0
[RR]
Shift logical left one or two bitl, clearing bit 0 (and bit 1 if Ihifting twice).
Table 2-2. CP1600 Instruction Set Summary (Continued)
STATUSES
TYPE MNEMONIC OPERAND lSi WORDS S Z C 0 OPERATION PERFORMED
L(D:(@]H15 - oiJ
RLC RRI.2) 1 x X X 2
[RR]
Rotate left one bit through Carry, or rotate 2 bits left through Overflow and Carry.
SLLC RRI.2) 1 X X X 2
~[[JH15'-
0 .... 0[RR]
Q Shift logical left one bit into Carry, clearing bit 0, or shift left two bits into Overflow and Carry,
w clearing bits 0 and 1.
:;)
~ a'
z SLR RRI.2) 1 x x 0 ... 15
i=
N
N
z 0 [RR]
9 Shift logical right.one or two bits, clearing bit 15 (and bit 14 if shifting twice) .
...
w~ SAR RRI.2) 1 X X
dj
. 0 '00(
a: w
"- [RR]
0
a: Shift arithmetic right one or two bits, copying high order bit.
w ~
4ciirm~15
..o~
II)
C; RRC RRI.2) 1 X X X 2
w a:
[RR]
Rotate right one bit through Carry, or rotate. two bits right through Overflow and Carry.
SARC RRI.2) 1 X X X 2
dE oK(2]M:D
[RR]
Shift arithmetic 'right one bit into Carry,. or two bits into Overflow and Carry.
SlNAP RRI.2) 1 X X
11,g D.
[RR]Swap bytes of register once, or twice.
':"
Table 2-2. CP1600 Instruction Set Summary (Continued)
STATUSES
1 Terminate current interrupt.
3 Jump to given address and enable interrupt system.
3 Jump to given address and disable interrupt system.
3 Jump to given address, saving Program Counter in R4, R5 or R6, and enable interrupt system.
3 Jump to given address, saving Program Counter in R4, R5 or R6, and disable interrupt system.
1 [RD<15,12»-[SW); [RD<7.4»-[SW)
Place Status Word in upper half of each byte of the specified register. RD may be RO, Rl, R2 or
1 Halt after executing next instruction.
1 Set double byte data mode for next instruction, which must be of one of the following types;
Primary or sacondary I/O or memory reference Immediate or immediate operate
If implied addressing through R I, R2, or R3 is used, the same byte will be accessad twice; address-ing through R4, R5, or R7 will give bytes from the addressed location and that addressed after auto-increment. Direct addressing and Stack addressing are not allowed in double byte mode.
Table 2-3. CP1600 Branch Conditions and Corresponding Codes
OBJECT CODE
MNEMONIC BRANCH CONDITION DESIGNATION
C C = 1 0001
LGT Carry
(logical greater than)
NC c=o 1001
liT No Carry
(logical less than)
OV 0= 1 0010
Overflow
NOV 0=0 1010
No overflow
PI.. s=o 0011
Plus
MI 5 = 1 1011
Minus
ZE Z = 1 0100
EO Zero (equal)
NZE Z =0 1100
NEQ Nonzero (not equal)
LT 5VO=1 0101
Less than
GE 5 .... 0=0 1101
Greater than or equal
LE ZV(5 .... 0) = 1 0110
Less than or equal
GT ZV(5 .... 0) =0 1110
Greater than
USC C .... S = 1 0111
Unequal sign and cany
ESC C .... 5 =0 1111
Equal sign and cany
The following notation is used in Table 2-4:
Where ten digits are shown. they are the ten low-order bits of a 10 to 16-bit word. (Word size depends on the system implementation.) Where four digits are shown. they represent the hexadecimal notation for an entire word (10 to 16 bits).
bb Two bits indicating one of the first three general purpose registers:
00 = RO 01 = R1 10 = R2
cccc Four bits giving the branch condition. as shown in Table 2-3.
ddd Three bits indicating a destination register. RD:
000 = RO 001 = R1 010 = R2 011 = R3 100 = R4 101 = R5 110 = R6 111 = R7
eeee Four bits giving the external branch condition. E. Control signals EBCAO-EBCA3 reflect the state of these four bits.
1111 One word of immediate data (10 or 16 bits)
2-23
mmm
m
p P rr
Three bits indicating a Data Counter Register RM:
000
=
RO 001=
Rl010
=
R2 all=
R3 100 = R4 101 = R5 110=
R6111
=
R7One bit indicating the number of rotates or shifts:
a
one bit position 1 two bit positions One bit of immediate addressOne hexadecimal digit (4 bits) of immediate address
Two bits indicating one of the first four general purpose registers:
00 = RO 01 = Rl 10 = R2 11 = R3
sss Three bits indicating a source register. RS:
000 = RO 001
=
Rl 010 = R2 011 = R3 100 = R4 101 = R5 110 = R6 111 = R7z Sign of the displacement:
a
add the displacement to PC contents 1 subtract the displacement from PC contentsIn the "Machine Cycles" column. when two numbers are given with one slash between them (e.g .. 7/9). execution time depends on whether or not a branch is taken. When two numbers are given. separated by two slashes (such as 81/11).
execution time depends on which register contains the implied address.
THE BENCHMARK PROGRAM
For the CP1600 our benchmark program may be illustrated as follows:
MVII IOBUF.R4 LOAD THE I/O BUFFER STARTING ADDRESS INTO R4 MVII TABLE.Rl LOAD THE TABLE STARTING ADDRESS INTO Rl MVI@ Rl.R5 LOAD ADDRESS OF FIRST FREE TABLE WORD INTO R5 MVII CNT.R2 LOAD WORD COUNT INTO R2
LOOP MVI@ R4.RO LOAD NEXT DATA WORD FROM 10BUF MVO@ RO.R5 STORE IN NEXT TABLE WORD
DECR R2 DECREMENT WORD COUNT
BNZE LOOP RETURN IF NOT END
MVO@ R5.Rl RETURN ADDRESS OF NEXT FREE TABLE BYTE
This benchmark program makes very few assumptions. The input table IOBUF and the data table TABLE can have any length. and can reside anywhere in memory. The address of the first free word in TABLE is stored in the first word of the TABLE.
Table 2-4. CP1600 Instruction Set Object Codes
MACHINE MACHINE
INSTRUCTION OBJECT CODE WORDS CYCLES INSTRUCTION OBJECT CODE WORDS CYCLES
ADCR RD 000010lddd 1 6 JSRE RB.LABEL 0004 3 12
CP1600