KIT – The Research University in the Helmholtz Association
MuPix8 – Large Area Monolithic HVCMOS Pixel Detector for the Mu3e Experiment
Alena Weber 1,2 , Heiko Augustin 2 , Niklaus Berger 3 , Sebastian Dittmeier 2 , Felix Ehrler 1 , Lennart Huth 2 , Mridula Prathapan 1 , Ivan Perić 1 , Rudolf Schimassek 1 , André Schöning 2 , Dirk Wiedner 2 , Hui Zhang 1
Highlights of MuPix8
Large area: 1 x 2 cm²
180 nm High Voltage CMOS (HVCMOS) technology on high resistivity wafers (AMS aH18)
128 columns, each with 200 pixels, monolithic readout Fast hit scan logic
New readout electronics with several readout modes for timewalk correction
Efficieny greater than 99.6%
Application of the MuPix in the Mu3e experiment
Requirements of the pixel detectors for the Mu3e experiment at PSI Vertex resolution: ~100 μm
Time resolution: 20 ns
Detector thickness: max. 50 μm
Can be achieved by HVCMOS technology
HVCMOS Technology
CMOS monolithic pixel sensors with depleted sensitive volume Monolithic means the sensor and the readout electronics are integrated on a single silicon chip
High voltage usage for fast charge collection and larger active area
Structure of MuPix8
The pixel matrix is divided into three submatrices with different signal transmission modes from pixel to readout
Submatrix A uses voltage signal transmission, submatrices B and C use current signal transmission
Fast Hit Scan Logic
MuPix8 uses a scan logic which allows a faster search for a hit The scan logic works with pixel groups, if a hit is detected in a group
the following groups are skipped
This leads to a faster hit transmission to the end of column
.
cell number
0 10 20 30 40 50
delay time (ns)
0 0.5 1 1.5 2
2.5 standard logic fast logic
1Karlsruhe Institute of Technology, 2University Heidelberg, 3University Mainz
New readout electronics with several readout modes
The MuPix8 has new readout electronics for timewalk correction Two comparators for each pixel are used
Timewalk Problem
The timestamp marks when the signal crosses the threshold voltage, however there is a delay between the particle hit and the threshold
crossing moment
This delay depends on signal amplitude and is called timewalk
The standard method for the timewalk correction is a ToT (time over threshold) measurement
Mode with two threshold voltages
The lower threshold voltage delivers a time- stamp with less timewalk
The higher threshold voltage confirms that the first timestamp belongs to a signal
Advantage: less timewalk, small noise rate
Mode with ADC threshold voltage
The constant threshold delivers the timestamp and activates the ramp signal
The ramp signal crosses the signal level,
delivering a second timestamp for amplitude information
Advantage: better linearity, less noise
Efficiency
In 2017, first testbeams with MuPux8 at DESY and at CERN were performed
Results show a high efficiency > 99.6% at 125 MHz clock
Outlook
A new HVCMOS pixel detector (MuPix9) has been submitted in 2017 to test the following improvements:
New slow control
New power regulators, to evaluate serial powering concepts Design of 2 x 2 cm2 chip ongoing
time voltage
threshold voltage
timewalk
time voltage
threshold 2 threshold 1
time voltage
constant threshold raising threshold
A B C
199
0 ...
...0 199 EOC
Pixels
Readout
End of column
199
0 ...
...0 199
199
0 ...
...0 199
EOC EOC
47 ... 0 47 ... 0 31 ... 0
Alena Weber Email: alena.weber@partner.kit.edu Phone: +49 721 608 26304
fastIn x1
!x2 x3
!x4
y2 y1
fastIn
!x1
!x2 select2 select1
x5
!x6
y3 y4 y6 y5
!x3
!x4
!x5
!x6
select3
select6 select5 select4
x7
!x8 x9
y8 y7 !x7
!x8 select8 select7 y9 !x9 select9
1 cm 2 cm
n-well
n-well p-well n-well
isolated NMOS isolated PMOS
collection electrode - deep n-well p-substrate
HV
time (ns)
300 400 500 600 700 800
number of electrons
1000 2000 3000 4000 5000 6000 7000
sigma linear fit
X-ray calibration with Fe, Zn, Mo, Ag targets test signal callibration for linearity check number of electrons
3000 4000 5000 6000 7000
400 500 600 700 800 900
40 60 80 100 120 140 160 180 0.8
0.95 0.9 0.95
1 Preliminary
efficiency
threshold (mV) 10 20 30 40
20 40 60 80 100 120 140 160 180
0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
efficiency
column (pixel)
row (pixel) time (ns)
KIT ASIC and Detector Laboratory
