The MuPix8 Chip A monolithic large scale pixel sensor
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(2) The Mu3e Experiment. Searching for the charged Lepton Flavor Violating decay µ+ → e + e − e + Recurl pixel layers Scintillator tiles. Inner pixel layers μ Beam. Target. Outer pixel layers. sensitivity goal of one in 1016 decays, requires high muon rates of 109 s−1 reconstruction of electron trajectories in a 1 T solenoidal magnetic field multiple coulomb scattering dominated (pe < 53 MeV/c). 19/03/18. MuPix8. Heiko Augustin. 2 / 13.
(3) High Voltage - Monolithic Active Pixel Sensor (HV-MAPS). E field. N-well P-substrate. Particle. I.Peric, P. Fischer et al., NIM A 582 (2007) 87. 19/03/18. low ohmic substrate (20 Ω cm - 200 Ω cm). depleted n-well diode. high voltage (−120 V). no additional readout chip. AMS 180nm HV-CMOS. thinned to 50 µm. MuPix8. charge collection via drift. Heiko Augustin. 3 / 13.
(4) Road to the first full scale Mu3e Pixel Sensor. MuPix8 MuPix10. 128 columns. pixel matrix 19.5 mm. MuPix7. submatrix A. First fully monolithic prototype. 32. 48. submatrix B. submatrix C. 200 rows. 48. digital periphery bias blocks & pads 10.8 mm. Scalability. MuPix9. Full scale Mu3e sensor chip. Detector Integration 19/03/18. MuPix8. Heiko Augustin. 4 / 13.
(5) MuPix8 Design Features 128 columns 48. 32. 48. pads on one edge improve time resolution. pixel matrix 19.5 mm. → flexprint readiness. submatrix A. submatrix B. submatrix C. 200 rows. 2 × 1 cm2 chip size. radiation hard design increase active volume (80 Ω cm substrate) digital periphery bias blocks & pads 10.8 mm. 19/03/18. MuPix8. Heiko Augustin. 5 / 13.
(6) MuPix8 Chip 128 columns. 128 × 200 pixels. pixel matrix 19.5 mm. 81 × 80 µm2 pixel size. 32. 48. submatrix A. submatrix B. submatrix C. 16 × 10 mm2 active area. 200 rows. 48. 3 matrix partitions digital periphery bias blocks & pads 10.8 mm. 19/03/18. MuPix8. Heiko Augustin. 6 / 13.
(7) MuPix8 Architecture Periphery Periphery Peripherybaseline. Pixel Pixel. sensor. State Machine State Machine State Machine. CSA comparator 1&2 readout. other pixels. x3 Pixel. .. .. 8b/10b encoder. tune DAC. test-pulse injection. readout state machine. VCO & PLL. serializer. LVDS LVDS LVDS. MUX. LVDS. threshold amplification. integrate charge. line driver. per pixel threshold adjustment. digital output. timewalk reduction circuitry 3 sub-matrices with dedicated data output additional merged data output. 19/03/18. MuPix8. Heiko Augustin. 7 / 13.
(8) Crosstalk and Signal Transmission. very dense routing: 2 metal layers, 200 signals 300 nm spacing 1 sub-matrix source follower 2 sub-matrices current driven. MuPix8. 19/03/18. MuPixX. MuPix8. Heiko Augustin. 8 / 13.
(9) Crosstalk and Signal Transmission. Pixel CSA. very dense routing: 2 metal layers, 200 signals 300 nm spacing. Bias Voltage. Bias Voltage. Periphery. Bias Voltage. Res. 1 sub-matrix source follower 2 sub-matrices current driven. Comparator. 19/03/18. MuPix8. Heiko Augustin. 8 / 13.
(10) Voltage. Pixel Digital Cell. Signal. 3 time walk correction approaches. Threshold2 Threshold1. Time Signal Thr1. Signal Thr2. 2 comparators. Comp. Hold TimeStamp. 5 tune bits + pixel switch. Comp. Store Timestamp & Hit Flag. 10(+6) timestamp bits. 2-threshold On-Chip correction. 19/03/18. MuPix8. Heiko Augustin. 9 / 13.
(11) Voltage. Pixel Digital Cell. Threshold. 3 time walk correction approaches. Baseline Dynamic Threshold. ToT Time. 2 comparators. Dynamic Threshold Signal. Comp. Thr. Start Ramp & Store Timestamp. Signal Dyn Thr. Comp. Store ToT Timestamp & Hit Flag. 5 tune bits + pixel switch 10(+6) timestamp bits. voltage ramp Off-Chip correction. 19/03/18. MuPix8. Heiko Augustin. 9 / 13.
(12) Pixel Digital Cell. 3 time walk correction approaches 2 comparators 5 tune bits + pixel switch 10(+6) timestamp bits. 19/03/18. MuPix8. Heiko Augustin. 9 / 13.
(13) Slow Control Interface - Status SIn Ld SOut. Ck1 Ck2. MuPix8. Rb. Ref_N Ref_P SyncRes_N SyncRes_P. DataOut_N DataOut_P. 6 single ended signals no chip address readback of DAC values ⇒ not feasible for module production with two layer flexprints 19/03/18. MuPix8. Heiko Augustin. 10 / 13.
(14) Slow Control Interface - Required Changes SIn_N. SOut. SIn_P. Chip Address <0:3>. MuPix9. Ref_N. +. Ref_P. DataOut_N DataOut_P. reduction of I/0 connections differential Inputs → solved using a SC Bus (Chip Address) readback of Chip Information via Data stream 19/03/18. MuPix8. Heiko Augustin. 11 / 13.
(15) Slow Control Interface - Required Changes Slow Control State machine. Control Signals SyncReset. SIn_N SIn_P. Receiver: 32 bit w/o 8b10b DC-Balance. Data Interpreter: 4bit Flag. Chip Address <0:3>. Ref_P. SOut. Tuning/Conf Readback. 4 bit Chip Address. Fast- Clk. SC - Clk. Ref_N. Bias DACs. >/. PLL & VCO. Clk. State machine: Readout, Serializer .... DataOut_N DataOut_P. reduction of I/0 connections differential Inputs → solved using a SC Bus (Chip Address) readback of Chip Information via Data stream 19/03/18. MuPix8. Heiko Augustin. 11 / 13.
(16) Slow Control Interface - The MuPix9. Reset. Waiting for Input. custom 32bit protocol. Read Input Signals. chip address. Sync Reset Interpret Data Word. Readback DAC. Write to DAC register. Readback ADC. Load DACs. Write to Pix Register. Load Pix Values. broadcast synchronous reset standalone and integrated available expected this summer. More on MuPix9 by Alena Weber (T 5.10). 19/03/18. MuPix8. Heiko Augustin. 12 / 13.
(17) Slow Control Interface - The MuPix9. custom 32bit protocol. Shunt 1. Shunt 2. Pixel Chip. chip address broadcast synchronous reset standalone and integrated available expected this summer. Standalone Slow Control Statemaschine. More on MuPix9 by Alena Weber (T 5.10). 19/03/18. MuPix8. Heiko Augustin. 12 / 13.
(18) Conclusion & Outlook 128 columns. pixel matrix 19.5 mm. 32. 48. submatrix A. submatrix B. submatrix C. 200 rows. 48. more to explore on MuPix8: Bandgap, merged link, ... many parts silicon proven design decisions have to be made start of MuPix10 design soon. digital periphery bias blocks & pads 10.8 mm. 19/03/18. MuPix8. Heiko Augustin. 13 / 13.
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