Nuclear Instruments and Methods in Physics Research A

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Results on 3D interconnection from AIDA WP3

Hans-Günther Moser

Max-Planck-Institut für Physik, Föhringer Ring 6, 80805 Munich, Germany

On behalf of AIDA-WP3

a r t i c l e i n f o

Article history:

Received 9 November 2015 Received in revised form 18 February 2016 Accepted 27 February 2016

Keywords:

3D integration ASICs

a b s t r a c t

From 2010 to 2014 the EU funded AIDA project established in one of its work packages (WP3) a network of groups working collaboratively on advanced 3D integration of electronic circuits and semiconductor sensors for applications in particle physics. The main motivation came from the severe requirements on pixel detectors for tracking and vertexing at future Particle Physics experiments at LHC, super-B factories and linear colliders. To go beyond the state-of-the-art, the main issues were studying low mass, high bandwidth applications, with radiation hardness capabilities, with low power consumption, offering complex functionality, with small pixel size and without dead regions. The interfaces and interconnects of sensors to electronic readout integrated circuits are a key challenge for new detector applications.

&2016 Published by Elsevier B.V.

1. Introduction

The main objective of WP3 work package of the AIDA project [1]was the demonstration of the feasibility of 3D interconnection of pixel detectors and readout electronics for applications in Par- ticle Physics. 3D integration for pixel sensors is driven by several motivations: one is the optimisation of the routing of the service connections. Classical hybrid pixel sensors have their I/O pads on the sensor (¼front) side making the connection difﬁcult and resulting in large dead space and material overhead. This can be solved by routing the I/O contacts to the back side of the readout electronics using a few vias at the periphery of the chip. In this case interconnection density is low and large diameter vias can be used. A more challenging goal is the reduction of the pixel size.

This needs high interconnection density and reduces the area available for in-pixel readout circuitry. Additional space can be gained by stacking layers of electronics on top of each other. This has the additional advantage that different technologies optimized for different tasks (sensing, analogue amplification, digital data processing) can be used. In these cases high density interconnection technology and low diameter vias are required. WP3 was pursuing different technological approaches to 3D integration like via-first/middle (vias are etched andfilled during the CMOS processing) orvia-lasttechniques (vias are processed after the com- pletion of the CMOS processing). Also, the pitch of the bonding interconnection between the layers of these 3D devices may vary

from moderately large values (of the order of 100

μ

^{m) to more}

aggressive ones (from a few tens of

μ

m down to few

μ

^m).

2. Sub-projects of AIDA WP3

Seven sub-projects performed by different member institutes of AIDA WP3 each investigated a different technological approach to 3D integration. Some of these projects used almost mature technologies with large diameter vias etched through the silicon (Through Silicon Via or TSV) which can be used at the chip periphery. Others aimed for a smaller interconnection pitch andﬁne, high aspect ratio TSVs which could eventually be used in the central pixel area of a chip. These challenging approaches had more risks but on the other hand pave the way for more advanced possibilities in future applications. The sub-projects will be described in more detail in the following. Some of them also had to adjust their goals, taking into account the availability and the reliability of the 3D technologies chosen.

The sub-project of Bonn University and CPPMtested an interconnection technique allowing the access to the wire bond pads of the 3D structures after ﬂip chip bonding. It used a via-last TSV process from Fraunhofer IZM [2] on ATLAS FE-I3 pixel readout wafers[3]. Processing of tapered TSV (100

μ

m diameter) at wafer level was successfully achieved. Demonstrator modules featuring planar sensors bump bonded to 90

μ

m thin FE-I3 with TSVs were built. Using the connection on the back-side these modules could be operated successfully.

TheCERNproject used Medipix3 chips[4]as the platform for 3D integration development utilizing an existing mature TSV Contents lists available atScienceDirect

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Nuclear Instruments and Methods in Physics Research A

http://dx.doi.org/10.1016/j.nima.2016.02.102 0168-9002/&2016 Published by Elsevier B.V.

E-mail addresses:hgm@hll.mpg.de,moser@mpp.mpg.de

Please cite this article as: H.-G. Moser, Nuclear Instruments & Methods in Physics Research A (2016), http://dx.doi.org/10.1016/j.

nima.2016.02.102i

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technology made available by CEA-LETI[5]. The LETI via-last process offers vias of about 40

μ

m diameter and 3:1 aspect ratio.

Wafers with the Medipix3 chips were post-processed by CEA-LETI.

In an X-ray imaging laboratory experiment, the CERN team was able to correctly read out by means of TSVs a MEDIPIX3.1 chip.

This chip was bump bonded to a 300

μ

m thick edgeless Si sensor from VTT/ADVACAM. The chip had a full redistribution layer on the back side to route the vias to pads for connection to a standard PCB. This development is a very important achievement as it points the way forward to tiling large areas seamlessly. LETI was able achieve a yield of 50% for perfect assemblies. Further successful assemblies were made with MEDIPIX chips thinned to 50

μ

^m.

TheINFN/IPHCsub-project initially aimed for design and fab- rication of a 3-tier pixel sensor resulting from the vertical interconnection of a dual-layer CMOS readout circuit to a third CMOS layer optimized for particle sensing or to an edgeless or 3D detector[6]. The 3D front-end electronics consisted of an analog layer and a digital layer provided by Globalfoundries (CMOS 130 nm)[7]and interconnected by Tezzaron[8]through copper- to-copper bonding and thermo-compression techniques. The design of the 128 32 matrix has been completed. However, access to the technology was not provided during the time frame of AIDA despite the promising results obtained with a multiproject wafer run organized by the 3D-IC consortium before the beginning of AIDA[9]. As an alternative a test of the T-Micro [10] vertical integration process using high density bump bonding was performed on existing readout chips (12832 channels) and n-on-n pixel sensors. The interconnection yield of front-end chip/pixel detector pairs was evaluated showing considerable variations from chip to chip: 1–24% of the interconnections were found not to work properly. Again the weak point of the project was the unavailability of the Tezzaron 3D integration process of the front-end chip. Because of these problems IPHC and INFN agreed to change the scope of the project and perform small pitch interconnection tests with Fraunhofer IMS [11]. Test vehicles were chips with CMOS sensors with MIMOSA-like analog readout electronics fabricated by Tower/Jazz[12]. A 3D structure will be fabricated with two layers of CMOS sensors with 10

μ

m pitch interconnections using a SLID (Solid–Liquid InterDiffusion) process.

The original plan of theLAL/LAPP/LPNHEproject was to interconnect ASICs in TSMC[13]65 nm technology to edgeless sensors.

The chips should be processed with TSVs either in the periphery or pixel by pixel. However, this was based on the assumption that TSMC 65 nm would become available through a CERN frame contract. Since this was accomplished only in mid 2014, the project could not be realized within AIDA.

TheMPPproject aimed for the interconnection of the new FE-I4 ATLAS chip [14] to a compatible sensor using a 3D technology developed by Fraunhofer EMFT[15]. The interconnection is based on the SLID process by EMFT, which has the potential of achieving 20

μ

m pitch or less. First studies of SLID with the ATLAS FEI3 chip were successful, achieving 100% interconnected pixels [16]. As next step, IZM is currently processing the new ATLAS FE-I4B chip.

The FE-I4B wire bonding pads have are designed to be compatible with TSVs such that a front-side processing step is not needed.

This is different from the FEI3 where a copper plug had to be placed in the via to connect it to the chip circuitry.

This aim of the project byBarcelona Universitywas to increase theﬁll factor of Geiger mode APDs (GAPD) by interconnecting two tiers of GAPDs using the Tezzaron via-ﬁrst process. The project could not be completed due to the unavailability of the Tezzaron process.

RAL/Uppsalaaimed to fabricate 3DIC ASICs with analogue and digital pixel readout cells stacked on top of each other and interconnected using the Fraunhofer EMFT SLID process. Wafers with 4040 pixel readout chips were built based on the Hexitec CZT circuitry[17]. A second digital chip contained an ADC in each pixel and the digital readout. There is one TSV interconnect from the analogue pixel to the digital pixel and one for each I/O connection as all readout is from the top layer. EMFT has processed TSVs and delivered a wafer of SLID bonded ASICs. However, the wafer was visibly poorly bonded and the yield appeared to be very low. Only 6 out of 9 devices remained connected together after dicing. In a different project a four-side-buttable version of the Hexitec chip was produced using large TSVs (70

μ

m) in the periphery. The TSV metal ﬁlling was copper connected to the Hexitec Al pad. The processing was performed successfully by T-Micro in Japan. Some problems occurred due to a rather high contact resistance in the I/

O pads and bending of the thinned ASICs.

3. Conclusions

The WP3 sub-projects sampled different technologies with different challenges. It could not be expected that all of them progress at the same pace. Some sub-projects were investigating 3D technologies which have the potential to lead to high-density interconnection but still had technological challenges. Others used more mature technologies but offer only large diameter vias which limit the possibilities for advanced designs. Those projects turned out to be the most successful ones, like the CERN project using a CEA-LETI process, Bonn/CPPM using the Fraunhofer IZM technology, and RAL/Uppsala with T-Micro. Basically this TSV technology is available and can be applied as a via-last technology to almost any ASIC.

On the other hand, projects which aimed for high density interconnections with high aspect ratio, narrow vias were less successful. The SLID technology was tried in three projects with mixed results. The same for TSVs: while EMFT failed with the tungstenfilling of narrow vias in the MPP project the identical technology worked for RAL/Uppsala. This indicates that the processes are not yet fully stable. The most advanced 3D processes use via-first technologies. Here one is bound to a specific ASIC technology and a vendor supporting this process. This was offered by Tezzaron. A proof of principle of the process could be achieved, nevertheless it became obvious that it is technically still very dif- ficult and not readily available.

Acknowledgments

The research leading to these results has received funding from the European Commission under the FP7 Research Infrastructures project AIDA, Grant agreement no. 262025.

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