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Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated

Equipment

Volume 650, Issue 1, 11 September 2011, Pages 145–149

International Workshop on Semiconductor Pixel Detectors for Particles and Imaging 2010

Performance of thin pixel sensors irradiated up to a fluence of and development of a new interconnection technology for the upgrade of the ATLAS pixel system

A. Macchioloa, , , L. Andriceka, b, M. Beimfordea, H.-G. Mosera, b, R. Nisiusa, R.H. Richtera, b, P. Weigella

a Max-Planck-Institut für Physik, Föhringer Ring 6, D-80805 München, Germany

b Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, D-81739 München, Germany

Available online 13 December 2010.

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http://dx.doi.org/10.1016/j.nima.2010.11.163, How to Cite or Link Using DOI

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Abstract

A new pixel module concept is presented, where thin sensors and a novel vertical integration technique are combined. This R&D activity is carried out in view of the ATLAS pixel detector upgrades. A first set of n-in-p pixel sensors with active thicknesses of 75 and has been produced using a thinning technique developed at the Max-Planck-Institut Halbleiterlabor (HLL). Charge Collection Efficiency measurements have been performed, yielding a higher CCE than expected from the present radiation damage models. The interconnection of thin n-in-p pixels to the FE-I3 ATLAS electronics is under way, exploiting the Solid Liquid Interdiffusion (SLID) technique developed by the Fraunhofer Institut EMFT. In addition, preliminary studies aimed at Inter-Chip-Vias (ICV) etching into the FE-I3 electronics are reported. ICVs will be used to route the signals vertically through the read-out chip, to newly created pads on the backside. This should serve as a proof of principle for future four-side tileable pixel assemblies, avoiding the cantilever presently needed in the chip for the wire bonding.

Keywords

Pixel detector; ATLAS; SLHC; SLID; ICV; Radiation hardness

1. Introduction

A novel module concept is being evaluated for the operation in the ATLAS pixel detector, in view of the foreseen luminosity upgrades of the LHC accelerator [1]. Ahead of the first phase, planned to start around 2016, the insertion of the fourth innermost pixel layer will be carried out. After the year 2020 the second phase of the upgrade will require a complete replacement of the ATLAS tracker detector. Thin planar pixel sensors (

) are among the candidate technologies to instrument the innermost layer of the new pixel system.

At the same applied voltage a higher electric field is present across thin detectors and, after high radiation levels, an increased Charge Collection Efficiency (CCE) is measured with respect to sensors with a standard thickness of [2]. For the application to the “Phase II” upgrade, the R&D activity presented here

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combines the thin planar pixel sensors with the vertical integration technology to obtain a more compact module design. Fig. 1 illustrates the module concept, with the Solid Liquid Interdiffusion (SLID) as an alternative to the bump-bonding interconnection, and Inter-Chip Vias (ICVs) to route signals and services to the backside of the read-out chip. The application of the vertical integration technology is studied in collaboration with the Fraunhofer Institute EMFT [3], where the SLID and ICVs techniques have been developed. The demonstrator module is being realized with the FE-I3 chip, due to the lack of availability for a chip designed to read-out the ATLAS pixel sensors and exploiting the 3D integration. The aim of this R&D activity is to prove the feasibility of the “via last” approach for particle physics applications, where ICVs are created after the fabrication of active circuitry and back-end layers but prior to dicing and assembly [4].

Fig. 1. Proposed module with thin sensors and ICV-SLID vertical integration technology. ICVs are etched on the chip pads originally designed for wire bonding.

View high quality image (94K)

2. Thin pixel sensors

The production of the n-in-p pixel sensors, with an active thickness of 75 or has been completed by the Semiconductor Laboratory (HLL) of the Max-Planck-Institut für Physik (MPP). The pixel geometry is such that it can be interfaced to a single FE-I3 chip. The method adopted for the production of these devices, developed at the MPP-HLL [5], starts from the oxidized high resistivity sensor wafer, where a back-side implantation is performed. Then the sensor wafer is bonded to a handle wafer through oxide-bonding and thinned to the desired thickness from the front-side. After polishing, the front-side processing and passivation are carried out.

Finally the handle wafer can be removed by deep anisotropic wet etching that allows for a selective removal of the carrier in well defined areas. For our present pixel production the handle wafer has not been etched away since it serves as a support during the ASIC interconnection procedure. Of the 8 n-in-p wafers completed with the method previously described, four have been diced and partially irradiated, while the remaining four have been left undiced because the SLID process requires several steps to be performed at the wafer level.

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2.1. Electrical characterization of thin pixel sensors

The FE-I3 compatible pixel sensors have been electrically characterized before and after irradiation with 26 MeV protons at the cyclotron of the Karlsruhe Institute of Technology (KIT). For both thicknesses the production yield has been excellent, with only one failing structure over of a total number of 80. Before irradiation the leakage currents, as shown in Fig. 2, resulted to be . The breakdown voltages have been measured to be in the range of 300–600 V, much higher than the maximum depletion voltage of 120 V, relative to the active thickness [6]. The electrical characterization after irradiation of the pixel devices up to a fluence of 1×1015 neq cm−2 has been reported in Ref. [6]. For the two highest fluences investigated, 3×1015 and 1016 neq cm−2 the characterization has been carried out using strip sensors from the same wafers as for the thin pixel devices. The strip pitch for these sensors is and the strip design differs from that of the pixels only by the length of 7 mm, given the fact that the strips are also DC-coupled and biased with a punch-through structure. These strip sensors have been subsequently used for CCE measurements, as described in Section 2.2. The leakage current characteristics, shown in Fig. 3, demonstrates the expected increase of the breakdown voltage after irradiation, and the possibility to operate these detectors at high bias voltages after heavy radiation doses. In both plots the red curves refer to the leakage currents measured after an annealing time of 80 min at 60 °C, with the expected decrease of their values with respect to the pre- annealing ones.

Fig. 2. Leakage currents characteristics of a subset of pixel sensors. Black curves with the full marker are relative to thick sensors while red curves with the open marker are relative to the thick sensors. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)

View high quality image (389K)

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Fig. 3. Leakage current characteristics of the strip sensors with an active thickness of (a) and (b), measured at T=

−10 °C after irradiation. The red curve (open markers) refers to the leakage currents measured after an annealing time of 80 min at 60 ° C. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)

View high quality image (753K)

2.2. CCE measurements on thin strip sensors

The interconnection of the thin pixel sensors to the read-out electronics has not been completed yet, so that the CCE for the thin devices has been evaluated using the strip sensors described in the previous section. The CCE has been measured in devices irradiated up to a fluence of 1016 neq cm−2 with 26 MeV protons. The detectors were read-out with the ALIBAVA acquisition system, based on the Beetle chip and working with the

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LHC speed electronics [7]. The CCE measurement set-up includes also a 90Sr source in combination with a scintillator trigger system, and it is installed in a climate chamber to allow for dark and cool operation down to

−46 °C. Two sensors were used to obtain a calibration of the expected signal size before irradiation for 75 and thick sensors. In both the devices the charge was measured in the plateau region, i.e. above the full depletion voltage. The leakage current, increasing linearly with the fluence, contributes to the shot noise of the system and can degrade the chip output signal linearity. Hence the measurements have been performed at

−30 °C or at −46 °C to keep the leakage current . For the thick detector irradiated at

3×1015 neq cm−2 and the thick detector irradiated at a fluence of 1016 neq cm−2 a pitch-adapter, designed at the University of Helsinki, has been used to decouple the leakage current from the Beetle chip input.

After high integrated fluences or for low bias voltages the signal spectrum is shifted towards smaller charge values and it becomes strongly affected by the noise. In order to extract the signal size, an algorithm has been developed to estimate and subtract the noise contribution to the total spectrum. For this, the noise shape is derived from random events that lie, as shown in Fig. 4, well outside a time window centered around the peaking time of the signal.

Fig. 4. Average pulse shape of a thick sensor before irradiation, biased at 100 V and operated at −30 °C. The time is calculated with respect to the trigger generated by the scintillator.

View high quality image (307K)

The normalization of the noise distribution is obtained from the ratio of the integrals of the first non-empty bins of the histogram obtained with the events in the signal region shown in Fig. 4, and the histogram obtained with events in the noise region. In case of the “signal events”, the first bins are in all cases dominated by the noise, as it is demonstrated by Fig. 5.

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Fig. 5. Collected charge for a thick sensor, irradiated at a fluence of 3×1015 neq cm−2, and biased at a voltage of 950 V.

View high quality image (176K)

An example of the spectrum resulting from the subtraction algorithm is illustrated in Fig. 6.

Fig. 6. Spectrum of a thick sensor, irradiated at a fluence of 3×1015 and biased at 200 V, obtained with the noise subtraction algorithm.

View high quality image (273K)

The results of the CCE measurements are shown in Fig. 7. The collected charge for the irradiated detector is normalized to the charge measured before irradiation for the corresponding active thickness. For each measurement the uncertainty was assumed to be 500e. This value has been estimated by various repetitions of the same measurement using different fit parameters, S/N requirements and temperatures. Within errors, the

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thick sensors can recover the full charge measured before irradiation up to the maximum fluence of the 1016 neq cm−2 fluence, when biased at voltages around 700 V. The thick sensors need voltages above 1000 V to achieve a CCE above 70% at a fluence of 3×1015. At 1400 V, the maximum voltage applied, the measured CCE is (83±4)%. The measurements for the thick sensors, irradiated at a fluence of 1016 neq cm−2, are still ongoing. The better CCE for thinner devices can be explained by their higher electric field for the same applied bias voltage, leading to an increased drift velocity and a lower trapping probability.

Anyhow the measurements for both active thicknesses at high applied bias voltages result in a CCE larger than expected from the calculations based on the current radiation damage models [8]. This effect has also been observed by other groups with devices irradiated at high fluences and it has been interpreted with the charge multiplication process taking place in the first microns below the n+ electrodes, in the area of highest electric field of the detectors [9] and [10].

Fig. 7. CCE measured after irradiation with strip-sensors of (a) and (b) active thickness. The band around each curve defines the uncertainty associated to the measurement, estimated to be 500e.

View high quality image (677K)

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3. Application of a vertical integration technology to the FE-I3 compatible pixels

3.1. The SLID interconnection

The SLID interconnection is investigated in the framework of the ATLAS pixel upgrade as a possible alternative to the bump-bonding technology. The sensor and chip preparation for SLID starts with the application of a 100 nm thin TiW diffusion barrier. The isolation of the last metal layer on the wafers is provided by a BCB coating (Benzocyclobuten, Cycloten), the openings therein define the contacts to the last layer. The choice of the BCB passivation is driven by the high degree of planarization that it offers and its higher electrical isolation capability with respect to SiO2. This second property answers the most severe isolation requirements of the n- in-p pixels, where the area outside the guard ring structure on the top side, facing the read-out chip, is at the same high potential of the backside.

The SLID process continues with the electroplating of a Cu layer to both sides. Only on one side a layer of tin is applied on top of the Cu layer. The same mask can be used both for the Cu and Sn deposition. To form the connection, the two devices are aligned, brought into contact and heated to a temperature of 240–320 ° C. At these temperatures the tin melts and diffuses into the copper to form an eutectic Cu3Sn alloy. The alloy has a melting point of around 600 °C and so does not melt during the SLID interconnections of subsequent layers, paving the way to a future multi-layer pixel assembly. Other advantages of the SLID technology are the possibility of having different shapes and sizes of the contact pads and the lower number of process steps than in the bump-bonding technology, that could finally result in a cost-reduction.

The possible influence of the SLID technology on the sensor properties has been investigated and no detectable effects have been observed [11].

The efficiency of the SLID interconnections, in a range of parameters relevant for the pixel sensors of tracking detectors, has been investigated by means of a test-production with daisy chains of different pad sizes and pitches. In particular the efficiency for the SLID pad geometry implemented in the thin pixel production, with dimensions of , has been estimated to be (5±1)×10−4[6].

The electroplating of the SLID pads has to be performed at the wafer level. This step has already been completed on one FE-I3 wafer and four sensor wafers, two for each active thickness, as a first step for the assembly of the demonstrator pixel modules. Fig. 8 shows the SLID pads created on the FE-I3 chip, either in the active part of the chip, to establish the electrical connection to the sensor counterpart or in the area where the end-of-column logic is located, to increase the mechanical stability of the assembly. The FE-I3 chips have

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been then singularized and reconfigured onto a 6 in. handle wafer, according to the location of the pixels in the MPP-HLL thin sensor production.

Fig. 8. View of the FE-I3 chip with the electroplated SLID pads. On the top part the pads are over the opening in the original passivation layer of each chip channel. In the bottom part additional SLID pads are placed in the area occupied by the end-of-column logic, to enhance the mechanical stability of the assembly.

View high quality image (823K)

A test assembly has been obtained using one handle wafer populated with FE-I3 chips and one dummy sensor wafer, where only the first oxide and an Aluminum layer have been deposited. Fig. 9 shows the cross-section of SLID pads in a FE-I3 module of this wafer. Two different phases of the Cu–Sn alloy are visible, Cu6Sn5 and Cu3Sn, with the latter being the more thermally stable one. The assembly is affected by a misalignment of about , originated by a rotation of the chips in the handle wafer with respect to their nominal position, measured to be in the range of 0.05–0.3°. This misalignment is much smaller than the pixel pitch, and the reduced size of the connection is still larger than the needed for a reliable SLID connection.

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Fig. 9. Cross-section of a FE-I3 pixel module, with a dummy sensor, where the interconnected SLID pads are shown. Two different phases of the Cu–Sn alloy are visible.

View high quality image (280K)

The SLID interconnection of the FE-I3 chips to the real thin pixel sensors is in preparation, with the chip to wafer technique employed in the test-assembly.

3.2. Inter Chip Vias

The Vertical Integration Technology also offers the possibility of extracting the signals from the backside of the read-out chip by using the Inter-Chip-Vias (ICV) process. The ICV technique is being applied for the read-out of the MPP thin pixel sensors connected to the FE-I3 read-out chips. The foreseen post-processing for the FE-I3 starts at wafer level with the etching of the vias on the chip pads originally designed for the wire bonding, after having removed the last aluminum layer. The positions of the ICVs on the pad are visible in Fig. 10(a) as defined by the mask needed for the first photolitographic step before the etching process. Around the ICVs a

wide trench is designed to provide an additional isolation of the vias belonging to different pads. The cross-section of a via is , with an initial depth of . They are passivated with tetraethyl orthosilicate and afterwards filled with tungsten in a chemical vapor deposition (CVD) process. As the FE-I3 wafers have an initial thickness of around they have to be thinned down from the back-side after the via filling until the vias are exposed. After the thinning, an additional process step is needed to form the metal contact pads on the back-side.

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Fig. 10. (a) Picture of the wire-bond pad on the FE-I3 chip with a photolitographic mask defining the position of the ICVs. The continuous line around the vias defines a trench inserted to provide an additional isolation of the vias belonging to different pads. (b) SEM picture of a slanted cross-section of a test-wafer with the vias etched in the configuration needed for the FE-I3 chip. The wider openings are the vias on two different rows, located at different depths. The narrower columns show a cross-section of the trench structure.

View high quality image (246K)

Etching trials have been performed on a test wafer to determine the optimal dimensions of the vias and the process sequence to etch through the different dielectrics layers of the FE-I3 chip. A SEM picture of one of these etching trials is shown in Fig. 10(b).

The R&D activity will continue with the SLID interconnection of the FE-I3 chips with ICVs to the thin pixel sensors, also in this case adopting the chip to wafer technique.

4. Conclusion

A first production of pixel sensors with an active thickness of 75 and has been completed in view of the ATLAS pixel detector upgrades. The electrical characterization before and after irradiation shows an excellent behaviour in terms of leakage currents and operability at high bias voltages. CCE measurements performed after irradiation show that it is possible to recover 100% of the charge obtained before irradiation in the thick sensors at a fluence of 1016 neq cm−2 and 83% of the charge in the thick sensors at a fluence of 3×1015 neq cm−2. Thin pixel sensors are being connected to FE-I3 chips using the SLID interconnection, a possible alternative to the bump-bonding technique. A high interconnection efficiency was measured with daisy chain structures for different pad sizes and pitches. The pixel sensor and chip wafers have been electroplated and a test assembly of real FE-I3 chips with a dummy sensor wafer has been completed. The post-processing of the ASIC wafers has started with etching trials to determine the optimal dimensions of the vias and process sequence.

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Acknowledgments

This work has been partially performed in the framework of the CERN RD50 Collaboration. The authors thank A. Dierlamm and the contribution of the Helmholtz Alliance for the sensor irradiation at the Forschungzentrum in Karlsruhe. We are grateful to J. Härkönen of the University of Helsinki for having provided us with the decoupling pitch-adapter used to connect the DC-coupled strip sensors in the CCE measurements.

References

[1]M. Lamont, LHC near and medium term prospects, in: Proceeding of Physics at the LHC 2010, Hamburg, 7–12 June

2010.

[2]G. Casse et al.

Nucl. Instr. and Meth. A, 624 (2010), p. 401

[3]Fraunhofer Institute EMFT: 〈http://www.emft.fraunhofer.de/index/Fraunhofer-EMFT/Fraunhofer-EMFT.html〉.

[4]P. Ramm, et al., 3D system-on-chiptechnologies for more than Moore systems, J. Microsys. Technol., 〈http://dx.doi.

org/10.1007/s00542-009-0976-1S〉, 2009, pp.1–5

[5]L. Andricek et al.

IEEE Trans. Nucl. Sci., NS-51 (3) (2004), p. 1117

[6]A. Andricek, et al., Development of thin sensors and a novel interconnection technology for the upgrade of the

ATLAS pixel system, Nucl. Instr. and Meth. A, 〈http://dx.doi.org/10.1016/j.nima.2010.04.087S〉, in press, doi:10.1016/j.nima.2010.04.087

[7]R. Marco-Hernandez et al.

IEEE Trans. Nucl. Sci., NS-56 (3) (2009), p. 49

[8]M. Beimforde, Ph.D. Thesis, TU München, 2010 〈http://publications.mppmu.mpg.de/2010/MPP-2010-115/FullText.

pdf〉.

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[9]G. Kramberger, et al., in: IEEE NSS Conference Record, N25-206, Orlando, USA, 2009.

[10]J. Lange et al.

Nucl. Instr. and Meth. A, 622 (2010), p. 49

[11]A. Macchiolo et al.

Nucl. Instr. and Meth. A, 591 (2008), p. 229

Corresponding author.

Copyright © 2010 Elsevier B.V. All rights reserved.

Abbildung

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Fig. 1. Proposed module with thin sensors and ICV-SLID vertical integration technology
Fig. 2. Leakage currents characteristics of a subset of pixel sensors. Black curves with the full marker are relative to   thick  sensors while red curves with the open marker are relative to the   thick sensors
Fig. 3. Leakage current characteristics of the strip sensors with an active thickness of   (a) and   (b), measured at T=
+6

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