Application of the DRS Chip for Fast Waveform Digitizing

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Application of the DRS Chip for Fast Waveform Digitizing

Stefan Ritt

Paul Scherrer Institute, Switzerland

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Question ?

4 channels 5 GSPS

1 GHz BW 8 bit (6-7) 15k$

4 channels 5 GSPS

1 GHz BW 8 bit (6-7) 15k$

4 channels 5 GSPS

1 GHz BW 11.5 bits 1k$

USB Power 4 channels 5 GSPS

1 GHz BW 11.5 bits 1k$

USB Power

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March 14th, 2009 TIPP09 Tsukuba 3

Switched Capacitor Array

Shift Register

Clock IN

Out

“Time stretcher” GHz  MHz

Waveform stored

Inverter “Domino” ring chain

0.2-2 ns

FADC 33 MHz

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Switched Capacitor Array

• Cons

• No continuous acquisition

• Limited sampling depth

• Nonlinear timing

• Pros

• High speed (6 GHz) high resolution (11.5 bit resol.)

• High channel density (9 channels on 5x5 mm

²

)

• Low power (10-40 mW / channel)

• Low cost (~ 10$ / channel)

t t t t t

Goa l: M inim ize Lim itati ons

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DRS4

•Designed for the MEG experiment at PSI, Switzerland

•UMC 0.25 m

1P5M MMC process (UMC), 5 x 5 mm², radiation hard

•8+1 ch. each 1024 cells

•Differential inputs, differential outputs

•Sampling speed 500 MHz … 6 GHz, PLL stabilized

•Readout speed

30 MHz, multiplexed or in parallel

I N 0 I N 1 I N 2 I N 3 I N 4 I N 5 I N 6 I N 7 I N 8

S T O P S H I F T R E G I S T E R R E A D S H I F T R E G I S T E R W S R O U T

C O N F I G R E G I S T E R R S R L O A D

D E N A B L E W S R I N D W R I T E

D S P E E D P L L O U T

D O M I N O W A V E C I R C U I T P L L

A G N D

D G N D A V D D

D V D D D T A P

R E F C L K

P L L L C K A 0 A 1 A 2 A 3

ENABLE

O U T 0 O U T 1 O U T 2 O U T 3 O U T 4 O U T 5 O U T 6 O U T 7 O U T 8 / M U X O U T B I A S O - O F S R O F S S R O U T R E S E T S R C L KS R I N

F U N C T I O N A L B L O C K D I A G R A M

M U X

WRITE SHIFT REGISTER WRITE CONFIG REGISTER

C H A N N E L 0 C H A N N E L 1 C H A N N E L 2 C H A N N E L 3 C H A N N E L 4 C H A N N E L 5 C H A N N E L 6 C H A N N E L 7 C H A N N E L 8

M U X L V D S

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How to minimize dead time ?

• Fast analog readout: 30 ns / sample

• Parallel readout

• Region-of-interest readout

• Simultaneous write / read

I N 0 I N 1 I N 2 I N 3 I N 4 I N 5 I N 6 I N 7 I N 8

S T O P S H I F T R E G I S T E R R E A D S H I F T R E G I S T E R W S R O U T

C O N F I G R E G I S T E R R S R L O A D

D E N A B L E W S R I N D W R I T E

D S P E E D P L L O U T

D O M I N O W A V E C IR C U I T P L L A G N D

D G N D A V D D

D V D D D T A P R E F C L K

P L L L C K A 0 A 1 A 2 A 3

ENABLE

O U T 0 O U T 1 O U T 2 O U T 3 O U T 4 O U T 5 O U T 6 O U T 7 O U T 8 / M U X O U T B I A S O - O F S R O F S S R O U T R E S E T S R C L K

S R IN

F U N C T I O N A L B L O C K D I A G R A M

M U X

WRITE SHIFT REGISTER WRITE CONFIG REGISTER

C H A N N E L 0 C H A N N E L 1 C H A N N E L 2 C H A N N E L 3 C H A N N E L 4 C H A N N E L 5 C H A N N E L 6 C H A N N E L 7 C H A N N E L 8

M U X L V D S

AD9222 12 bit 8 channels

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ROI readout mode

readout shift register

Trigger stop

normal trigger stop after latency

Delay

delayed trigger stop

Patent pending!

33 MHz

e.g. 100 samples @ 33 MHz

 3 us dead time

 300,000 events / sec.

e.g. 100 samples @ 33 MHz

 3 us dead time

 300,000 events / sec.

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Daisy-chaining of channels

Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave

1 clock

0 1 0 1 0 1 0

enable input

Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave

1 clock

0

1 0

enable input

DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells Chip daisy-chaining possible to reach virtually unlimited sampling depth

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Simultaneous Write/Read

Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7

0

FPGA

0 0 0 0 0 0 0

1 ^{Channel 0}

Channel 1

1

Channel 0 readout

8-fold

analog multi-event buffer

Channel 2

1

Channel 1

0

Expected crosstalk ~few mV Expected crosstalk ~few mV

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Trigger an DAQ on same board

• Using a multiplexer in DRS3, input signals can simultaneously digitized at 65 MHz and sampled in the DRS

• FPGA can make local trigger (or global one) and stop DRS upon a trigger

• DRS readout (6 GHz samples) though same 8-channel

FADCs

analog front end

DRS FADC

12 bit 65 MHz

MUX FPGA

trigger

LVDS

SRAM

DRS4

global trigger bus

“Free” local trigger capability without additional hardware

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DRS4 Performance

Test Results

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Bandwidth

Bandwidth is determined by bond wire and internal bus resistance/capacitance:

850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip)

850 MHz (-3dB)

QFP package _final

bus width

Simulation Measurement

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Timing jitter

t₁ t₂ t₃ t₄ t₅

• Inverter chain has transistor variations

 t_i between samples differ

 “Fixed pattern aperture jitter”

• “Differential temporal nonlinearity”

TD_i= t_i – t_nominal

• “Integral temporal nonlinearity”

TI_i = t_i – it_nominal

• “Random aperture jitter” = variation of t_i between measurements

• Inverter chain has transistor variations

 t_i between samples differ

 “Fixed pattern aperture jitter”

• “Differential temporal nonlinearity”

TD_i= t_i – t_nominal

• “Integral temporal nonlinearity”

TI_i = t_i – it_nominal

• “Random aperture jitter” = variation of t_i between measurements

TD₁ TI₅

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Fixed jitter calibration

• Fixed jitter is constant over time, can be measured and corrected for

• Several methods are commonly used

• Most use sine wave with random phase and correct for TD_i on a statistical basis

• Fixed jitter is constant over time, can be measured and corrected for

• Several methods are commonly used

• Most use sine wave with random phase and correct for TD_i on a statistical basis

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Sine Curve Fit Method

S. Lehner, B. Keil, PSI i

j



 







 ⁵⁰⁰

0 1024

0

2

2 2 ) )) min

sin(

( (

j i

j j

j

ji o

i f a

y   



yji : i-th sample of measurement j

a_j f_j _j o_j : sine wave parameters

i : phase error  fixed jitter

“Iterative global fit”:

• Determine rough sine wave parameters for each measurement by fit

• Determine _i using all measurements where sample “i” is near zero crossing

• Make several iterations

“Iterative global fit”:

• Determine rough sine wave parameters for each measurement by fit

• Determine _i using all measurements where sample “i” is near zero crossing

• Make several iterations

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Fixed Pattern Jitter Results

• TD_i typically ~50 ps RMS @ 5 GHz

• TI_i goes up to ~600 ps

• Jitter is mostly constant over time,

 measured and corrected

• Residual random jitter 3-4 ps RMS

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Applications of the DRS4 Chip

What can we do with this technology?

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Flash ADC Technique

60 MHz 12 bit Q-sensitive

Preamplifier PMT/APD

Wire

Shaper

• Shaper is used to optimize signals for “slow” 60 MHz FADC

• Shaping stage can only remove information from the signal

• Shaping is unnecessary if FADC is fast enough

• All operations (CFD, optimal filtering, integration) can be done digitally

• Shaper is used to optimize signals for “slow” 60 MHz FADC

• Shaping stage can only remove information from the signal

• Shaping is unnecessary if FADC is fast enough

• All operations (CFD, optimal filtering, integration) can be done digitally

FADC

TDC

5 GHz 12 bit Transimpedance

Preamplifier FADC

PMT/APD Wire

Digital Processing Amplitude

Time Baseline

Restoration

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How to measure best timing?

Simulation of MCP with realistic noise and different discriminators Simulation of MCP with realistic noise and different discriminators

J.-F. Genat et al., arXiv:0810.5590 (2008)

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On-line waveform display

click template

fit

pedestal histo

⁸⁴⁸

PMTs

“virtual oscilloscope”

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Pulse shape discrimination

 

) t t [...]θ..

) t d θ(t

)/τ t e (t

/τ ) t e (t

/τi ) t e (t

A

V(t) ⁰ ⁰ ⁰   ₀   ₀  _r

  

 

 



  B s C

Leading edge Decay time AC-coupling Reflections

Example: / source in liquid xenon detector (or: /p in air shower) Example: / source in liquid xenon detector (or: /p in air shower)

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-distribution







_

= 21 ns



_

= 34 ns

Waveforms can be clearly distinguished



_

= 21 ns



_

= 34 ns

Waveforms can

be clearly

distinguished

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Template Fit

• Determine “standard” PMT pulse by

averaging over many events  “Template”

• Find hit in waveform

• Shift (“TDC”) and scale (“ADC”) template to hit

• Minimize ²

• Compare fit with waveform

• Repeat if above threshold

• Store ADC & TDC values

 Experiment 500 MHz sampling

Pile-up can be detected if two hits are separated in time by ~rise time of signal Pile-up can be detected if two hits are separated in time by ~rise time of signal

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Timing Big Systems I

Global Clock

~20 MHz

Reference Clock for DRS4 PLL

2.5 MHz

Reference Clock for

timing channel

LMK03000 Clock Conditioner (National Semiconductor) LMK03000 Clock Conditioner

(National Semiconductor) Jitter: 400 fsJitter: 400 fs

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Timing Big Systems II

Channel 0 Domino Wave

Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8

LMK03000 PLL Experiment wide

global clock DRS4

Chip

• Global clock locks all Domino Waves

to same frequency and phase

• Residual random jitter: 25 ps

• Even better timing can be obtained by clock sampling

• MEG Experiment: Single LVDS clock distributed over 9 VME crates

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Experiments using DRS chip

MAGIC-II 400 channels DRS2 MAGIC-II 400 channels DRS2 MEG 3000 channels DRS2

upgraded to DRS4 soon MEG 3000 channels DRS2 upgraded to DRS4 soon

BPM for XFEL@PSI

1000 channels DRS4 (planned)

MACE (India) 400 channels DRS4 (planned)

PET PET

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Availability

• DRS4 can be obtained from PSI on a “non-profit” basis

• Delivery “as-is”

• Costs ~ 10-15 USD/channel (1000-1500 JPY)

• USB Evaluation board as reference design

• VME boards from industry in 2009

32-channel

65 MHz/12bit digitizer

“boosted” by DRS4 chip to 5 GHz

32-channel

65 MHz/12bit digitizer

“boosted” by DRS4 chip to 5 GHz

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Conclusions

• Fast waveform digitizing with SCA chips will have a big impact on experiments in the next future

• DRS4 has 6 GHz, 1024 sampling cells per channel, 9

channels per chip, 11.5 bit vertical resolution, 4 ps timing resolution

• ~4000 DRS channels already used in several experiments, hope that other experiments can benefit from this

technology

http://drs.web.psi.ch

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Datasheet

http://drs.web.psi.ch/datasheets http://drs.web.psi.ch/datasheets

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Signal-to-noise ratio (DRS3!)

“Fixed pattern” offset error of 5 mV RMS

can be reduced to 0.35 mV by offset correction in FPGA

SNR:

1 V linear range / 0.35 mV = 69 dB (11.5 bits)

“Fixed pattern” offset error of 5 mV RMS

can be reduced to 0.35 mV by offset correction in FPGA

SNR:

1 V linear range / 0.35 mV = 69 dB (11.5 bits)

ANALOG OUTPUT [V]

BIN NUMBER

0 200 400 600 800 1000

0.48 0.49 0.5 0.51 0.52

Crosstalk from trigger signal

OCCURENCE

OUTPUT VOLTAGE [V]

0.48 0.49 0.5 0.51 0.52

0 20 40 60 80 100 120 140 160 180 200

OCCURENCE

OUTPUT VOLTAGE [V]

0.48 0.49 0.5 0.51 0.52

0 20 40 60 80 100 120 140 160 180 200

Offset Correction

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Interleaved sampling

delays (167ps/8 = 21ps)

G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)

6 GSPS * 8 = 48 GSPS

Possible with DRS4 if delay is implemented on PCB Possible with DRS4 if delay is implemented on PCB

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Latch Latch Latch Latch

Constant Fraction Discr.

Latch

12 bit

Clock



+ +

MULT

Latch

 0

&

<0

Delayed signal Inverted signal Sum