The DRS2 Chip: A 4.5 GHz Waveform Digitizing Chip for the MEG Experiment

The DRS2 Chip:

A 4.5 GHz Waveform Digitizing Chip for the MEG Experiment

Stefan Ritt

Paul Scherrer Institute, Switzerland

The MEG Experiment at PSI

1 m

e⁺

L i q . X e S c i n t i l l a t i o n D e t e c t o r



D r i f t C h a m b e r L i q . X e S c i n t i l l a t i o n

D e t e c t o r

e⁺



T i m i n g C o u n t e r S t o p p i n g T a r g e t

T h i n S u p e r c o n d u c t i n g C o i l M u o n B e a m

D r i f t C h a m b e r

• Stopped  beam of 10⁷-10⁸ s^-1, 100% duty factor

• Liquid Xe calorimeter for  detection

• Solenoidal magnetic spectrometer

• Radial drift chambers for e⁺ momentum determination

• Timing counter for e⁺

• Stopped  beam of 10⁷-10⁸ s^-1, 100% duty factor

• Liquid Xe calorimeter for  detection

• Solenoidal magnetic spectrometer

• Radial drift chambers for e⁺ momentum determination

• Timing counter for e⁺

E

= 52.8 MeV

Kinematics



= 180°

E

= 52.8 MeV

e 



Goal:

 → ^e 

at 10

Waveform Digitizing

Needed:

• Pile-up rejection (BG from 10⁸ µ decays in unsegmented

calorimeter)

• ADC dynamic range of 12 bit

• TDC resolution of 40 ps

• Analog pipeline (L1 trigger) ~300ns

• 3000 channels

Needed:

• Pile-up rejection (BG from 10⁸ µ decays in unsegmented

calorimeter)

• ADC dynamic range of 12 bit

• TDC resolution of 40 ps

• Analog pipeline (L1 trigger) ~300ns

• 3000 channels

t PMT

sum

51.5 MeV

0.511 MeV

~100ns

10 Bit 2 GS

100€/Chn

The DRS chip: principle of operation

0.2-1 ns

Inverter (“Domino”) chain Rotating

signal Input 1

Output 1 Input 2

Channels 3 to 10

Output 2

Domino Ring Sampler Domino

Ring

Sampler

Design of Inverter Chain

PMOS > NMOS

PMOS < NMOS

“Tail Biting”

enable

1 2 3 4

1

2

3

4

Domino Speed Control

U

U

U

U

• Two independent voltages to control domino wave speed

• U

used to select speed range

• U

used for fine-adjustment

• Need to compensate temperature and V

drifts

• Two independent voltages to control domino wave speed

• U

used to select speed range

• U

used for fine-adjustment

• Need to compensate temperature and V

drifts

Current mode readout

• First implemented in DRS2 (DRS1 had charge readout)

• Sampled charge does not leave chip

• Current readout less sensitive to charge injection and cross-talk

• First implemented in DRS2 (DRS1 had charge readout)

• Sampled charge does not leave chip

• Current readout less sensitive to charge injection and cross-talk

write

read

(200fF)

C

. . .

(700

R

I V

V

Timing Reference

signal

20 MHz Reference clock

PMT hit

Domino stops after trigger latency

8 in pu ts

shift register Reference

clock

domino wave

MUX

Domino speed stability of 10

:

The DRS2 Chip

• Fabricated in 0.25  m 1P5M MMC process (UMC), 5 x 5 mm

• Radiation Hard (CMS Pixel library, R. Horisberger)

• 10 channels (8 data + 2 calibration), each 1024 bins (300 ns analog delay + 100 ns signal at 2.5 GHz)

• Maximal sampling speed 4.5 GHz

• Readout speed 40 MHz

• Submitted to UMC in November 2003, 58 chips (400 channels) received in March 2004

• Packaged chip costs:

• 35 € / chn. (MPW run)

• Fabricated in 0.25  m 1P5M MMC process (UMC), 5 x 5 mm

• Radiation Hard (CMS Pixel library, R. Horisberger)

• 10 channels (8 data + 2 calibration), each 1024 bins (300 ns analog delay + 100 ns signal at 2.5 GHz)

• Maximal sampling speed 4.5 GHz

• Readout speed 40 MHz

• Submitted to UMC in November 2003, 58 chips (400 channels) received in March 2004

• Packaged chip costs:

• 35 € / chn. (MPW run)

• 3 € / chn. (engineering run)

Domino Circuit

Readout Shift Register

DRS2 Test Results

Preliminary !

Measured DRS2 Parameters

• Linear response up to 400mV

• Usable range of 1V p-p

• Linear response up to 400mV

• Usable range of 1V p-p

• Speed range

0.5 GHz – 4.2 GHz

• Speed range

0.5 GHz – 4.2 GHz

Linear approximation

PLL Stabilization

PLL

V

Reference Clock Domino Wave Pulse

~200 psec

~200 psec

R. Paoletti, N. Turini, R. Pegna R. Paoletti, N. Turini, R. Pegna

• Unstabilized jitter: ~70ps / turn

• Temperature coefficient: 500ps / ºC

• Unstabilized jitter: ~70ps / turn

• Temperature coefficient: 500ps / ºC

Frequency stabilization

V

16-bit LUT DAC

FPGA

Frequency Counter

• Compensate for temperature drifts

• Change Vspeed only between events, keep stable during acquisition phase

• Jitter ~ 150ps

• Timing accuracy with 9th channel < 25ps

• Compensate for temperature drifts

• Change Vspeed only between events, keep stable during acquisition phase

• Jitter ~ 150ps

• Timing accuracy with 9th channel < 25ps

150ps

Estimated Bandwidth

• Input pulse rising time: 0.9 ns

• Sampled at 2.5 GHz: 0.4 ns / sample

• Reconstructed rise time: 3 samples → 1.2 ns

• Estimated BW » 500 MHz

• Limited by protection diodes 40 MHz readout clock

Direct DRS2 output

DAQ Boards

DRS

R. Paoletti, N. Turini, R. Pegna MAGIC collaboration

USB

PSI GVME Board

FPGA with

4 Power-PC

Digitized Signals

• 7 ns pulses 500 mV

• Digitized at 2.5 GHz with USB test board

• 7 ns pulses 500 mV

• Digitized at 2.5 GHz with USB test board

• Pulses are nicely reproduced

• Analog inputs not properly terminated

• Non-constant response over

• Pulses are nicely reproduced

• Analog inputs not properly terminated

• Non-constant response over 1024 cells (parasitic R of

mV

Signal-to-noise ratio

mV

• 1 V DC input signal, common mode subtracted

• Individual bin has RMS of 2 mV → SNR = 500:1 (9 bit)

• Integration over 100 ns PMT pulse (250 bins) has RMS of

0.16 mV → SNR = 6200:1 (12.6 bit)

• Could be improved by better

analog design of Mezzanine board

• 1 V DC input signal, common mode subtracted

• Individual bin has RMS of 2 mV → SNR = 500:1 (9 bit)

• Integration over 100 ns PMT pulse (250 bins) has RMS of

0.16 mV → SNR = 6200:1 (12.6 bit)

• Could be improved by better

analog design of Mezzanine board

Waveform Analysis

• MEG: 3000 channels, 100 Hz, 1024 samples → 600 MB/sec

• Compress “interesting” and pile-up events in FPGA ( → 10x)

• Fit “background” events in PC farm (~10 PCs) with individual PMT response functions, derive multi-hit ADC and TDC data

• Overall data rate ~2 MB/sec

• MEG: 3000 channels, 100 Hz, 1024 samples → 600 MB/sec

• Compress “interesting” and pile-up events in FPGA ( → 10x)

• Fit “background” events in PC farm (~10 PCs) with individual PMT response functions, derive multi-hit ADC and TDC data

• Overall data rate ~2 MB/sec

 Experiment 500 MHz sampling

Next generation: DRS3

DRS1 DRS2 DRS3

Estimated

First tested November 02 March 04 Fall 05

Number of channels 1 10 10 (all differential)

Number of cells/channel 768 1024 1024-8192

MIN sampling speed (GHz) 0.7 0.5 0.5

MAX sampling sped (GHz) 2.5 4.5 4.5

Readout Speed (MHz) 20 40 40

Readout Dead Time (µsec) 40 256 (1024 samples) 10 (40 samples)

Signal to Noise ratio (bit) - > 12 (250 samples) > 12

Power Consumption (mW) 25 50 50

?

Conclusions

• Successful design of DRS2 with 8 x 1024 bins, running at 4.5 GHz

• Deploy ~200 channels in MEG Experiment in spring 2005

• Use DRS2 for drift chamber readout

• Final version (DRS3, 3000 channels) in 2006

• Not specific to MEG, useful for other experiments

• Successful design of DRS2 with 8 x 1024 bins, running at 4.5 GHz

• Deploy ~200 channels in MEG Experiment in spring 2005

• Use DRS2 for drift chamber readout

• Final version (DRS3, 3000 channels) in 2006

• Not specific to MEG, useful for other experiments