Application of the 5 GS/s Waveform Digitizing Chip DRS4
Roberto Dinapoli, Ueli Hartmann, Stefan Ritt † - Paul Scherrer Institute, Switzerland
IN0 IN1
OUT0 OUT1
33 MHZ CLK
REFShift Register Shift Register
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The DRS4 Chip
Experiments using DRS Chips
Evaluation Board
Ethernet Board (planned)
IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8
STOP SHIFT REGISTER
READ SHIFT REGISTER WSROUT
CONFIG REGISTER RSRLOAD
DENABLE WSRIN DWRITE
DSPEED PLLOUT
DOMINO WAVE CIRCUIT PLL AGND
DGND AVDD
DVDD DTAP REFCLK
PLLLCK A0 A1 A2 A3
ENABLE
OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8/
MUXOUT BIAS O-OFS ROFS SROUT RESET SRCLKSRIN
MUX
WRITESHIFTREGISTER WRITECONFIGREGISTER
CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 CHANNEL 8
MUX LVDS
Simplified Schematic
Four Channel Oscilloscope with USB power and readout
PC Oscilloscope Application (Windows and Linux) Basic Parameters
Functional Block Diagram
MEG (PSI) 3000 Channels
MAGIC-II (La Palma) 400 Channels
XFEL BPM (PSI) 800 Channels
MACE (India) 2400 Channels
Pre- amp
Pre- amp
DRS4 ADC FPGA PHY GBit Ethernet
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8 Channel board to be mounted directly on detector electronics 50 mm x 100 mm Preamplifier for PMTs, APDs, SiPMTs Read out through Gigabit Ethernet Local LVDS bus for cascading and synchronization
Event rate: 100 kHz (50 Samples/chn.) Goal: < 40 € /channel
†
corresponding author: stefan.ritt@psi.ch
Can be obtained from PSI
Technology:
Numer of Chn.:
Power:
Sampl. Speed:
Bandwidth:
Readout time:
Nonlinearity:
SNR:
Aperture jitter:
UMC 0.25 m with cells cascadable up to 8192
/chn. @ 2.5V 200 MSPS to
(-3dB) 30 ns * n 0.5*10 at 1V range
after calibration at 5 GSPS after calibration
m
samples -3
