Fast Waveform Digitizing in Radiation Detection using Switched Capacitor Arrays

Fast Waveform Digitizing in Radiation Detection using Switched Capacitor Arrays

Stefan Ritt

Question ?

4 channels 5 GSPS

1 GHz BW 8 bit (6-7) 15k$

4 channels 5 GSPS

1 GHz BW 8 bit (6-7) 15k$

4 channels 5 GSPS

1 GHz BW 11.5 bits 1k$

USB Power 4 channels 5 GSPS

1 GHz BW 11.5 bits 1k$

USB Power

The need for speed

Det chan

Q-ADC

Disc.

TDC Trigger

• Traditional technique

• Gated charge ADCs

• Constant Fraction Disc.

• Time-to-Digital Conv

.

• High rate applications

• Pile-up becomes an issue

 Waveform digitizing

• Issues: Limited speed and resolution

• High channel counts

• Power consumption

• FADC Costs

Det chan FADC

Moving average baseline

hits

Needed: >3 GSPS 12 bit

Switched Capacitor Array

Shift Register

Clock IN

Out

“Time stretcher” GHz  MHz

“Time stretcher” GHz  MHz

Waveform stored

Inverter “Domino” ring chain

0.2-2 ns

FADC 33 MHz

DRS4

•Designed for the MEG experiment at PSI, Switzerland

•UMC 0.25 m

1P5M MMC process (UMC), 5 x 5 mm², radiation hard

•8+1 ch. each 1024 cells

•Differential inputs, differential outputs

•Sampling speed 700 MHz … 5 GHz, PLL stabilized

•Readout speed

30 MHz, multiplexed or in parallel

I N 0 I N 1 I N 2 I N 3 I N 4 I N 5 I N 6 I N 7 I N 8

S T O P S H I F T R E G I S T E R R E A D S H I F T R E G I S T E R W S R O U T

C O N F I G R E G I S T E R R S R L O A D

D E N A B L E W S R I N D W R I T E

D S P E E D P L L O U T

D O M I N O W A V E C I R C U I T P L L

A G N D

D G N D A V D D

D V D D D T A P

R E F C L K

P L L L C K A 0 A 1 A 2 A 3

ENABLE

O U T 0 O U T 1 O U T 2 O U T 3 O U T 4 O U T 5 O U T 6 O U T 7 O U T 8 / M U X O U T B I A S O - O F S R O F S S R O U T R E S E T S R C L KS R I N

F U N C T I O N A L B L O C K D I A G R A M

M U X

WRITE SHIFT REGISTER WRITE CONFIG REGISTER

C H A N N E L 0 C H A N N E L 1 C H A N N E L 2 C H A N N E L 3 C H A N N E L 4 C H A N N E L 5 C H A N N E L 6 C H A N N E L 7 C H A N N E L 8

M U X L V D S

Comparison with other chips

MATACQ D. Breton

LABRADOR G. Varner

DRS4 this talk Bandwidth (-3db) 300 MHz > 1000 MHz 950 MHz

Sampling frequency 50 MHz…2 GHz 10 MHz … 3.5 GHz 700 MHz … 6 GHz

Full scale range ±0.5 V +0.4 …2.1 V ±0.5 V

Effective #bits 12 bit 10 bit 11.5 bit

Sample points 1 x 2520 9 x 256 9 x 1024

Frequency PLL YES NO YES

Digitization 5 MHz N/A 30 MHz

Readout dead time 650 s 150 s 3 s – 370 s

Integral nonlinearity ± 0.1 % ± 0.1 % ± 0.05%

Radiation hard No No Yes (chip)

Board V1729 (CAEN) - V17xx (CAEN)

Switched Capacitor Array

• Pros (DRS4 chip)

• High speed (5 GHz) high resolution (11.5 bit resol.)

• High channel density (9 channels on 5x5 mm

)

• Low power (10-40 mW / channel)

• Low cost (~ 10$ / channel)

• Cons

• No continuous acquisition

• Limited sampling depth

• Nonlinear timing

t t t t t

Goa l: M inim ize Lim itati ons

How to minimize dead time ?

• Fast analog readout: 30 ns / sample

• Parallel readout

• Region-of-interest readout

• Simultaneous write / read

I N 0 I N 1 I N 2 I N 3 I N 4 I N 5 I N 6 I N 7 I N 8

S T O P S H I F T R E G I S T E R R E A D S H I F T R E G I S T E R W S R O U T

C O N F I G R E G I S T E R R S R L O A D

D E N A B L E W S R I N D W R I T E

D S P E E D P L L O U T

D O M I N O W A V E C IR C U I T P L L A G N D

D G N D A V D D

D V D D D T A P R E F C L K

P L L L C K A 0 A 1 A 2 A 3

ENABLE

O U T 0 O U T 1 O U T 2 O U T 3 O U T 4 O U T 5 O U T 6 O U T 7 O U T 8 / M U X O U T B I A S O - O F S R O F S S R O U T R E S E T S R C L K

S R IN

F U N C T I O N A L B L O C K D I A G R A M

M U X

WRITE SHIFT REGISTER WRITE CONFIG REGISTER

C H A N N E L 0 C H A N N E L 1 C H A N N E L 2 C H A N N E L 3 C H A N N E L 4 C H A N N E L 5 C H A N N E L 6 C H A N N E L 7 C H A N N E L 8

M U X L V D S

AD9222 12 bit 8 channels

ROI readout mode

readout shift register

Trigger stop

normal trigger stop after latency

Delay

delayed trigger stop

Patent pending!

33 MHz

e.g. 100 samples @ 33 MHz

 3 us dead time

 300,000 events / sec.

e.g. 100 samples @ 33 MHz

 3 us dead time

 300,000 events / sec.

Daisy-chaining of channels

Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave

1 clock

0 1 0 1 0 1 0

enable input

enable input

Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave

1 clock

0

1 0

1 0

1 0

enable input

enable input

DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells Chip daisy-chaining possible to reach virtually unlimited sampling depth

DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells Chip daisy-chaining possible to reach virtually unlimited sampling depth

Simultaneous Write/Read

Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7

0

FPGA

0 0 0 0 0 0 0

1 ^{Channel 0}

Channel 1

1

Channel 0 readout

8-fold

analog multi-event buffer

Channel 2

1

Channel 1

0

Expected crosstalk ~few mV Expected crosstalk ~few mV

Interleaved sampling

delays (167ps/8 = 21ps)

G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)

6 GSPS * 8 = 48 GSPS

Possible with DRS4 if delay is implemented on PCB Possible with DRS4 if delay is implemented on PCB

Trigger and DAQ on same board

• Using a multiplexer in DRS4, input signals can simultaneously digitized at 65 MHz and sampled in the DRS

• FPGA can make local trigger (or global one) and stop DRS upon a trigger

• DRS readout (5 GHz samples) though same 8-channel

FADCs

analog front end

DRS FADC

12 bit 65 MHz

MUX FPGA

trigger

LVDS

SRAM

DRS4

global trigger bus

“Free” local trigger capability without additional hardware

“Free” local trigger capability without additional hardware

Performance of SCA Chips

Test Results

Bandwidth

• Passive Input: Bandwidth is determined by bond wire and internal bus resistance/capacitance:

850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip)

• Active Inputs: ~300 MHz with current CMOS technology (MATACQ)

• Near future: 130 nm technology might improve this slightly

850 MHz (-3dB)

QFP package

Measurement

Timing jitter

t₁ t₂ t₃ t₄ t₅

• Inverter chain has transistor variations

 t_i between samples differ

 “Fixed pattern aperture jitter”

• “Differential temporal nonlinearity”

TD_i= t_i – t_nominal

• “Integral temporal nonlinearity”

TI_i = t_i – it_nominal

• “Random aperture jitter” = variation of t_i between measurements

• Inverter chain has transistor variations

 t_i between samples differ

 “Fixed pattern aperture jitter”

• “Differential temporal nonlinearity”

TD_i= t_i – t_nominal

• “Integral temporal nonlinearity”

TI_i = t_i – it_nominal

• “Random aperture jitter” = variation of t_i between measurements

TD₁ TI₅

Fixed jitter calibration

• Fixed jitter is constant over time, can be measured and corrected for

• Several methods are commonly used

• Most use sine wave with random phase and correct for TD_i on a statistical basis

• Fixed jitter is constant over time, can be measured and corrected for

• Several methods are commonly used

• Most use sine wave with random phase and correct for TD_i on a statistical basis

Fixed Pattern Jitter Results

• TD_i typically ~50 ps RMS @ 5 GHz

• TI_i goes up to ~600 ps

• Jitter is mostly constant over time,

 measured and corrected

• Residual random jitter (RMS)

• 25 ps MATACQ

• 10 ps Labrador

• 3-4 ps DRS4

 SCA technology can

replace high resolution TDCs

 SCA technology can

replace high resolution TDCs

Applications of SCA Chips

What can we do with this technology?

On-line waveform display

click template

fit

pedestal histo

⁸⁴⁸

PMTs

“virtual oscilloscope”

“virtual oscilloscope”

Pulse shape discrimination

 

) t t [...]θ..

) t d θ(t

)/τ t e (t

/τ ) t e (t

/τi ) t e (t

A

V(t) ^{0 0 0}   ₀   ₀  _r

  

 

 



  B s C

Leading edge Decay time AC-coupling Reflections

Example: / source in liquid xenon detector (or: /p in air shower) Example: / source in liquid xenon detector (or: /p in air shower)

-distribution







= 21 ns



= 34 ns

Waveforms can be clearly distinguished



= 21 ns



= 34 ns

Waveforms can

be clearly

distinguished

Template Fit

• Determine “standard” PMT pulse by

averaging over many events  “Template”

• Find hit in waveform

• Shift (“TDC”) and scale (“ADC”) template to hit

• Minimize ²

• Compare fit with waveform

• Repeat if above threshold

• Store ADC & TDC values

 Experiment 500 MHz sampling

Pile-up can be detected if two hits are separated in time by ~rise time of signal Pile-up can be detected if two hits are separated in time by ~rise time of signal

Experiments using DRS chip

MAGIC-II 400 channels DRS2 MAGIC-II 400 channels DRS2 MEG 3000 channels DRS4

MEG 3000 channels DRS4

BPM for XFEL@PSI

1000 channels DRS4 (planned)

MACE (India) 400 channels DRS4 (planned)

MACE (India) 400 channels DRS4 (planned)

PET PET

Datasheet

http://drs.web.psi.ch/datasheets http://drs.web.psi.ch/datasheets

Evaluation Board

• DRS4 can be obtained from PSI on a “non-profit” basis

• Delivery “as-is”

• Costs ~ 15-20 CAN$/chn

• USB Evaluation board as reference design

• Anybody wants to build a pocket scope?

Conclusions

• This is Exciting Stuff!

• DRS4 has 6 GHz, 1024 sampling cells per channel, 9

channels per chip, 11.5 bit vertical resolution, 4 ps timing accuracy, other chips similar

• More development in the pipeline

• Fast waveform digitizing with SCA chips will have a big impact on particle detection in the next future

• Other fields should benefit from this development

LABRADOR: http://www.phys.hawaii.edu/~idlab/

MATACQ: http://matacq.free.fr/

DRS4: http://drs.web.psi.ch