The Central Frace s sor has a Uni-Record Interface which has a character- serial trunkline. This trunkline handles magnetic tape transports, punched card readers and punches, and line printers. The Uni-Record Interface has its own control section which can execute operations, once started, in parallel with program execution. Data transfers are character parity checked.
The Uni-Record Trunkline has the capability of off-line operations, namely, tape-to-card, card-to-tape, tape-to-line printer and card-to-lineprinter, under manual control.
1. 8 CHECKING FEATURES.
Reliability has been a primary aim in the data processing system design. When errors occur, they are caught by the character parity check that accompanies every data transfer by the Central Processor. Where possible, illegal characters are regarded as errors, such as in arithmetic operations and in memory addresses.
As part of the Disc Memory, 1/0, and Uni-Record Interface operations, the Central Processor program receives an interrupt signal upon remote detection of parity error in data transfers either way. Under program control, an override of the automatic termination of data transfers upon error detection is provided as an aid in error corrections.
Blocks, as stored in the Disc Memory, have the character parity bits stripped from them, but longitudinal parity bits substituted, for reasons of speed and economy.
Character parity is regenerated during transfer to the Central Processor.
Section I Paragraphs 1. 9 to 1. 10 A basic protection of stored data is provided by using the duplexed system to dupli-cate operations and stored data. This concept is carried to a finer level by the feature called "twinning", available both in Core Memory and Disc Memory.
Information is simultaneously stored in duplicate when in twin mode. In event of failure of one read operation, the second copy is still available.
The normal result of a sensed error is a program interrupt, unless this interrupt is ignored. The interrupt program can test for the detailed source of the error to take remedial action.
1. 9 DUPLEXING.
In a duplexed or multiplexed system, system functioning can be maintained by a single Central Processor. Program controlled cross connections are provided between Central Processors and Disc Memory Trunklines.
Each Display Console can be switched manually to either side of a duplex system.
Similarly, Buffer Processors may be switched, and have duplicate standby equip-ment available.
Each Central Processor is able to test by program the state of each switch. In addition, special communication is available between Central Processors for pro-grammed switching.
L 10 PROGRAM INTERRUPTS.
The Central Processor has an elaborate set of program interrupts. These provide a transfer of control to special programs which determine and deal with the causes of the interrupts and then resume normal program execution.
There are six classes of interrupts, each with an independent special program starting point. These classes are: Error, Disc Memory, Input, Real Time, Uni-Record, and Other Processor. Within each class are several detail interrupt sources which are program testable.
The Error class of interrupts has two divisions, Computer Error, which includes data transfer, arithmetic and program errors, and Interface Error, which includes Disc Memory, 110 Interface, and Uni-Record Interface errors.
The other classes of interrupts contain signals generated when specific action is to be taken as, for instance, when an interface finishes a data transfer operation.
All detail interrupt requests are stored in toggles which are reset by program individually or by class, and which can also be set by program.
Section I
Paragraph 1.10
Other toggles, under program control, permit ignoring interrupt requests by class, subclass, or totally, but without losing the interrupt requests which remain program testable.
SECTION II
Section II Paragraphs 2. 1 to 2. 1. 2
CORE MEMORY AND WORD FORMAT
Core Memory for the Data Processing System is provided in modules of 4000 words.
These modules may be assigned to a Central Processor on an individual basis, or may be connected to two Central Processors via a shared memory trunkline. The assigmnent of module addresses is by a patchboard, which has the additional facility of pairing module s in the Twin mode.
2. 1 MEMORY REGISTERS.
2. 1. 1 MEMORY ADDRESS REGISTER.
Words in each Core Memory module have decimal addresses of
0000
through3999.
Each module has an address register which is loaded in parallel via the trunk from the Central Processor, while the high order bits of the high order character of the address perform module selection through the patchboard. (In some units, two modules share a common address register.) The Memory Address register appears to the Central Processor as a single register. The Memory Address register re-ceives word addresses in parallel from the Program Control Section and the Disc Memory, Uni-Record and
Ilo
Interfaces. Parity is not checked, but an error is indicated when a non-existing memory module is addressed.2.1.2 MEMORY ACCESS REGISTER (M).
Each Core Memory module has an eight-character (full word) M register. (In some units, two modules share a common M register.) Transfers to or from Core Mem-ory are full word parallel, via the trunkline which appears to the Central Processor as a single Memory Access Register, which is displayed on the Central Processor Control Panel. All transfers are character parity checked.
Memory cycle time is 5 microseconds, and data is on the trunkline 2. 5 microseconds after the start of the cycle. For some operations Core Memory is half cycled for read only or write only. For instance, a half cycle write is performed when an ad-dress of four characters is to be stored into a word of memory, leaving the rest of the word unchanged. The effect is a saving of time where, otherwise, two full mem-ory cycles would be needed; a read-restore, and a clear-write. The sequence is half cycle read, modify, half cycle write. Half cycling is under tight logical control
Section II
Paragraphs 2. 2 to 2. 2. 3
so that, even under error conditions, no information will ever be lost. Other than effects on timing, programming is not involved in half cycling by any possibilities of over-writing or inadvertently clearing portions of memory.
A special feature allows overlap of memory cycles in different Core Memory mod-ules. The overlap gives an effective cycle time of about 4 microseconds. This cycle overlap is particularly effective in unrelated operations, such as the memory cycles requested by interfaces and their effect on normal program execution.
2. 2 SPECIAL FEATURES.
2. 2. 1 CYCLE DEMAND PRIORITY.
The Disc Memory, I/O, and Uni-Record Interfaces operate independently of, and simultaneously with, the Program Control Section. Any or all may be requesting a memory cycle. A precedence occurs at logic level giving priorities as follows:
a. 110 Interface.
b. Disc Memory Interface.
c. Uni-Record Interface.
d. Program Control Section.
Central Processor program instruction execution can wait the most easily, and is given the lowest priority.
2.2.2 INDIVIDUAL MEMORY TRUNKLINE.
Each Central Processor has an individual Memory Trunkline which can service up to eight memory modules. The assignment of a module to a Trunkline is done physi~.
cally by attaching cable s.
Memory modules are contained in cabinets that hold up to four modules and two sets of Trunkline Drivers. Each Trunkline Driver can connect one Trunkline with up to three memory modules. Pairs of modules which share common Address and M registers cannot be connected to separate Trunklines.
2.2.3 SHARED MEMORY TRUNKLINE.
Each Central Processor has a Shared Memory Trunkline. A single Central Proces-sor can service up to eight additional ~emory modules via this Trunkline. Two such Trunklines from two Central Processors can be connected together through a Shared Memory Switch built into the memory cabinet, and a total of up to eight
Section II Paragraph 2. 2. 4 memory modules can be distributed on either side of the switch. When the Shared Memory Switch is closed, a single Shared Memory Trunkline is formed, servicing all of the memory modules on either side of the switch, and only one Central Proc-essor has preemptive use of the Trunkline. That Central Processor also has ex-clusive program control of the switch. When the switch is open, each Central Processor can independently access the memory modules on its side of the switch.
Either Central Processor can control the Shared Memory Switch, and have access to all of the Shared Memory, and that Central Processor has Control Status. Con-trol Status is indicated to each Central Proces sor by its ConCon-trol Status toggle, which can be program tested (Z Y
=
59) and reset, but not set. The Control Status toggles in the two Central Processors are cross connected so that, when one is reset by program, the other is set, which transfers Control Status. Control Status also has an effect on the control of Disc Memory Duplexing, (Section XII).Each Central Processor has a program testable, settable, and resettable toggle (Z Y
=
31) that requests opening and closing of the Shared Memory Switch. Only the Request Memory Switch toggle in the Central Processor that has Control Status, affects the Shared Memory Switch. The Shared Memory Switch status is separately testable (ZY=
32). Switching will follow within 10 microseconds after changing the Request toggle.When one Central Processor is shut down, the other has full use of Shared Memory and the Shared Memory Switch remains closed. The Memory Switch Status will test closed (true). These conditions will persist until after power is reapplied to the shut down Central Processor.
2.2.4 MODULE ADDRESS PATCHBOARD.
Each Central Processor has a small Patchboard, figure 2-1, with which its memory module addresses are established. Each of the sixteen groups of 4000 addresses
('/J'/J'/J'/J0
through 63999) is presented as a selection signal that can be patched (con-nected) to any memory module, including all of those on the Shared Memory Trunk-line. Memory modules are numbered'/J
through 7 on the Individual MemoryTrunkline and 8 through 15 on the Shared Memory Trunkline.
Shared Memory modules can be assigned module addresses independently by the Patchboards in the two Central Processors. That is, a given module mayor may not have the same address patched to it in the two Central Processors.
Section II
STRAIGHT ADDRESS MEMORY TWIN
ADDRESS
00000 - 03999 GISPOCl
0 0 0 0
GISPTOCl GSTO(JP3
04000-07999
0
GSI(J0 0 0 0
GISPTI Cl0
08000 - 11999
o
GS2C0 0 0 0
12000 - 15999
o
GS3(J GlSP3 Cl0 0 0 0
GST3(J0
ISOOO -19999
0
GS4(J P2 GISP4(J0 0
GST4(J0
20000 - 23999 GISP50