L-119 MODULE DESCRIPTION

A block diagram of the L-ll9 Module is shown in figure 6-7. The L-l19 Module operates under control of its internal program.

Programs can be entered manually into the L-l19 Modules through the maintenance panel, or by the use of a manually inserted bootstrap program through one of the standard input devices. A. program entry device (not part of Buffer Processor) allows more efficient use of the program storage in the machine and also faster entry of a program.

6.5. I INPUT /OUTPUT INTERFA.CE.

A.lI data lines between a Data Link and the L-119 Modules are terminated at the Input/Output Interface in each L-119 Module. The Interface consists principally of timing and level standardizing circuits which ensure elect rical compatibility between the Data Link and each L-119 Module.

The L-119 Modules communicate with the Central Processor through the I/O

Interface in the Central Processor, Section V. This Interface selects a particular L-119 Module and designates the operation to be performed.

Section VI.

ORIGIN WORD CLOCK DECODING INFORMATION

LOGIC DECODING

6. 5. 2 DISC MEMORY.

Section VI Paragraph 6. 5. 2

The Disc Memory consists of a 7-inch diameter disc lTIounted on the shaft of an 8000 rpm motor. The disc is coated with a nickel-cobalt alloy which possesses optimum lTIagnetic and wear characteristics. The top plate of the disc housing is the mounting surface for 10 read/write heads and 6 write heads which run in contact with the lTIemory disc. These heads record or read from the 10 memory tracks.

The three recirculating register tracks each use one write head and one read/ write head, as do the permanent storage tracks. The remaining four timing tracks each use one read/write head.

For program and data storage, the Disc Memory has the following memory tracks:

a. Message Track b. Program Track

c. Working Storage Track d. Jump Address Track e. Data Field Track

f. Buffer Processor Word Marker Track g. Central Processor Word Address Track h. Clock Track

i. Origin Pulse Track j. Index Marker Track

The Message track serves as intermediate storage for input or output message data.

The Message track is a 336-word circulating register. It occupies one half of a disc track and is circulated twice per disc revolution.

The ProgralTI track holds two complete copies of the program, each occupying one half of the track. Each program consists of up to 336 L-119 Module words. Allow-ing for a space bit between L-119 Module words, the total storage around the disc is 6, 048 bits per track.

The Working Storage track is a fast access scratch pad. It uses one head for read-ing and one head for writread-ing. The heads, which are placed eight words apart, cir-culate the contents of the working storage, thus permitting access to each word once every eight word tilTIes.

Section VI

Paragraph 6. 5. 3

The Jump Addres s track specifies a jump addres s for the Table Look Up and recog-nition type instructions. It has one read/ write head. This track is the same length as the Program track.

The Data Field track is a 336-word permanent storage track which is accessible to the A register (read only). Each word from the Data Field track has nine bits, in-cluding parity.

The Buffer Processor Word Marker track provides an indication of the end of each L- 119 Module word. It has orie read/ write head. This track has a 1 recorded on it for every nine L-119 Module clock pulses. The primary use of the word marker pulse is to signal instruction termination and to gate the next instruction from the lower rank to the upper rank of the Instruction register.

The Central Processor Word Address track has recorded on it an address for each Central Processor word (one address per eight L-119 Module word times). The ad-dres ses on this track are used when transferring data between the L-119 Modules and the Central Processor. All data transferred between theL-119 Modules and the Central Processor is stored on the Message track. The Message track is 336 words in length (42 Central Processor words). The Central Processor Word Ad-dress track contains binary-coded adAd-dresses from f/J to 41 for the 42 Central Proc-essor words of Mes sage track storage. This track has one read/ write head.

The Clock track contains the L- 119 Module clock. The clock frequency of the L- 119 Modules is 800kco The Clock track has one read/ write head.

The Origin Pulse track provides an indication of the start of each of the recorded programs on the disc. A pulse recorded on this track coincides with the start of each of the programs on the Program track. One read/ write head is associated with this track.

The Index Marker track is a 336-word circulating register. This track contains an indexing bit which controls program execution timing both in the Normal mode and the One-Step mode. This bit is movable under program control.

6. 5. 3 MAJOR LOGICAL ELEMENTS.

In addition to the Disc Memory and Input/ Output Interface, each L- 119 Module con-sists of the following major logical sections:

a. A register - The A register is a one-word (8 bit) accumulator for all arith-metic instructions, as well as being the central information exchange location

Section VI Paragraph 6.5.3 (Cont.) within the L- 119 Module. Parity is checked on all transfers to the A register, and odd parity is generated in the ninth bit position on all transfers from the A register, except for transfers to or from the memo registers.

b. B register - The B register is a one word (8 bit) register that is used as a counter in the Compare instruction for branching to a specified location. Also, the B register is a holder for a successful table look up operation.

c. Instruction register - The Instruction register is a one word (8 bit), double ranked register. The upper rank holds the instruction presently being executed while the lower rank is being loaded with the next instruction. During spacer bit time, the next instruction is gated from the lower to the upper rank of the Instruc-tion register.

d. Input/ Output register - The Input/ Output register is a one word (8 bit) regis-ter that serves as a buffer between the input or output device and the A regisregis-ter.

e. Memo registers -Memo 1 and 2 registers monitor the state of both the Data Link and Central Processor Interface control functions. Both are 8 bit registers with no parity and are accessible only to the A register. Memo 2 register also has the function of communication with another L-119 Module.

f. Message Track register - The Message Track register (MTR) is used pri-marily as a read-write buffer between the A register and the Message track. Also, the MTR is an address holder for message track transfer and for marker bit con-trol. Since read-write timing is dependent on the location of the Message Track marker, the Message Track register operates automatically when the proper

in-struction is given. The Message Track register holds nine bits, including parity, but will write only the first eight bits of a character onto the Mes sage track.

g. Add-Subtract Logical Control Section - The Add-Subtract Logical Control Section contains the logic necessary to perform the required algebraic functions of the instructions.

h. Marker Detection Logic - The marker detection logic is used with the Mes-sage track. A marker indicates the correct position for writing into or reading from the Mes sage track. The marker is located in the ninth bit position (1. e., the spacer bit position) of a word.

When a word is to be read from the Message track to the MTR, the Message track is scanned for the marker. Upon detecting the ma'rker (1. e., ninth bit set ON), the

Section VI

Paragraphs 6. 5. 4 to 6. 5. 5

marker control logic gates the following word from the Message track into the MTR and ~dvances the marker one word position.

When a word is to be written onto the Message track from the MTR, the Message track is scanned for the marker. Upon detecting the marker, the marker control logic gates the data from the MTR through the write amplifier into the following word position on the Message track and advances the marker by one (8 bit) word.

6.5.4 BUFFER PROCESSOR WORDS.

The Buffer Processor (L-119 Module) wo rd contains eight bits plus an odd parity bit. The instruction word format is as follows:

SOURCE OR

PARITY COMMAND DESTINATION

9 8 7 .6 5 4 3 2 1

Bits 1 through 4 designate the source or destination of information being operated upon or the mode of the command. A Central Processor character is contained in one Buffer Processor word. A Central Processor word is contained in eight Buffer Processor words.

6D 5. 5 MEMORY ADDRESSES.

The two basic types of L-119 memory addresses are: L-119 word addresses and message addresses. In addition, an address field is used that is called a mode.

This mode is a command modifier qccupying the address portion of the instruction word.

The content of an addres sed word consists of 8 bits plus a parity bit, except for the Memo 1 and 2 registers which do not carry parity. Register content is acces-sible from the A register which is the central transfer location within the L-119 Module. Table 6-1 shows the Buffer Processor word address assignments.

Table 6-1. L- 119 Module Word Addresses

x1 0tl00

Memo 1 Register

1

0tl01

Working Storage Track

2

tltlltl

Message Track Register

3

tl,Oll

Data Field Track

4 5 6 7

Section VI Paragraph 6. 5. 6

Table 6-1. L-119 Module Word Addresses (Cont)

fJl¢¢

,Ol~l ,011,0 pIll

A Register

Input/ Output Register Memo 2 Register B Register

Message addresses refer to the content of the various permanent storage tracks or to the I/O Interface in the Central Processor and may include up to 336 Buffer Proc-essor words of information. Table 6-2 shows the message address assignments.

Table 6-2. Message Addresses

¢ fJf),O,O Central Proces sor

1 riri,e)l Program Track

2 riD

1(i

Jump Address Track

3

¢¢ll

Data Field Track

In normal programming, no address but that of the Central Processor would be used. The other addresses are used only for original entry of program and data.

All address locations in table 6-2 are accessible from the Message track.

Address locations 1 through 3 all have nine bits per word including parity. The Message track word is eight bits with no parity bit since the ninth bit position is used for the Message Track marker. When data is transferred- from the Message track to these locations, a parity bit is generated and added in the ninth bit position.

6.5.6 MEMO ASSIGNMENTS.

Memo bit assignments are as shown in table 6-3.

Table 6-3. Memo Register Assignments

BIT MEMO 1 REGISTER MEMO 2 REGISTER

1 Character Present Message Track Busy

2 Device Ready

3 Message Available

Section VI

Paragraph 6.5.6 (Cont.)

Table 6-3. Memo Register Assignments (Cont)

BIT MEMO 1 REGISTER MEMO 2 REGISTER

4 Transfer Operation Acknowledge Transfer Ready

5 Internal Error Acknowledge Transfer

6 Interface Error Acknowledge Transfer

7 Acknowledge Transfer

8 Acknowledge Transfer

Individual memo bits are testable, by bringing in a bit from a memo register into the A register, through use of a Logical Product instruction with the appropriate·

bit. The single bit (toggle) in the A register can then be compared with a word in the Data Field track. Individual memos can be set by a Store instruction from the A register through an appropriate mask in the Data Field track.

The Character Present Memo toggle indicates that an input character is present in the Input Holder and is accessible to the Input/ Output register. It is automatically set but must be reset by program.

The Device Ready Memo toggle indicates that a character can be output to the Out-put Holder from the InOut-put/ OutOut-put register. It must be set by program but is auto-matically reset when the Output Holder is cleared.

The Transfer Operation Memo toggle is a signal on a line indicating that the Central Processor has accessed the L-119 Module. This line is not settable by the L-119 Module.

The Message Available Memo toggle is program settable and indicates to the Central Processor that a message is available on input or that a message slot is available on output. It is automatically reset by the Central Processor when the message trans-fer has been completed.

The Internal Error Memo toggle is automatically set upon detection of an instruction word parity error, an input parity error to A, or a message transfer parity error from the Central Processor. It can also be set under program control, if any pro-gram detected inconsistency occurs.

The Interface Error Memo toggle is set automatically upon detection of a parity error in the Input Holder. It is also settable under program control..

Section VI Paragraph 6. 6 The Message Track Busy Memo toggle indicates that a Message Track instruction should not be given. It is set and reset automatically.

The Acknowledge Transfer Ready Memo toggle is set by a Receiving L-119 to indi-cate to a Sending L-119 that an acknowledge code is ready to be transferred from the Receiving L-119. The four Acknowledge Transfer Bit Memo toggles can transfer up to 16 codes from a Receiving L-119 to a Sending L-119.

The Memo toggles labelled Open can be used in any way desired by the programmer.

Im Dokument General Precision, (Seite 128-136)