The Program Control Section provides the registers and control circuitry that en-able the Central Processor to carry out the specified instructions. Each
Section III Paragraphs 3.2.1 to 3.2.2 instruction is obtained from Core Memory in the location specified as the instruc-tion address and is held and processed in the Instrucinstruc-tion register which is de-scribed in terms of its component parts.
3.2. 1 INSTRUCTION ADDRESS REGISTER (Ia).
The Instruction Address register (Ia) is a four-character static register that pro-vides the address for instruction access. The normal address format is as
follows: The numeric bits of the three least significant characters, and bits 1 and 2 of the fourth character, specify locations
00'1J'/J
through 3999 for each Core Mem-ory module. Bits 3 through 6 of the fourth character provide a binary value of0
through 15 that select one of 16 Core Memory modules. Since the fourth character carries a binary value of0
to 63, Core Memory addresses can be thought of as running from00000
to 63999.The Ia register counts up by one after instruction execution, unless its content was affected by a program jump, paragraph 4. 5. A program jump places the fully modified operand address in the Ia register to be used for the next instruction access.
The Ia register content can be changed by a Load (Ea) or Copy (=) instruction, para-graphs 4.2.6 and 4.2. 8. In case of Ia register change, one is added to the result-ing Ia content before the next instruction access. Transfers to and from Ia are in four character parallel.
The Ia register content will count up from 63999 to
00000,
but instruction execution is halted and an End of Memory Error Interrupt request is generated. Should the Ia register count up to a non-existent address (one for which there is no Core Memory module), the Core Memory control rejects the address and generates an Illegal Address Interrupt request. The content of the Instruction Address register is displayed on the Central Processor Control Panel.3.2.2 OPERAND ADDRESS REGISTER (Oa).
The Operand Address register (Oa) is a four-character static register that holds the operand address through the execution of an instruction. The address is held in normal format, paragraph 3. 2. 1.
The Operand Address register is first loaded with the address portion, MMMM, of the instruction word, paragraph 2.4.4. Options that may modify the operand address then take place. These are: Index Modify, paragraph 2.4.3, Indirect
Section III
Paragraphs 3.2.3 to 3.2.5
Addressing, paragraph 2.4.5. 1, and PDPM, paragraph 3.4. MASM, para-graph 3.5, does not modify Oa. Transfers to and from Oa are in four character parallel.
If the modified operand address specifies a non-existent memory module, and a memory cycle is required, an Illegal Address Interrupt request is generated (unless the memory cycle is required, no interrupt is requested). Interrupt re-quests may occur also during execution of instructions that require multi-word Core Memory accesses. The latter may also generate End of Memory Interrupt requests.
The Operand Address register content can be transferred to another register by a Copy instruction. In this case, it is the original address portion of the Copy in-struction itself that is transferred. The Operand Address register can be trans-ferred into by a Copy instruction, but will have its content replaced by the next
instruction. The content of the Operand Address register is displayed on the Central Processor Control Panel.
3.2.3 INDEX HOLDER (Xh).
The Index holder (Xh) is a one -character static register that holds the six-bit in-dex character of each instruction and selects Inin-dex register operation. For inin-dex operation, refer to paragraph 2.4. 3. The content of the Index holder is displayed on the Central Processor Control Panel.
3.2.4 COMMAND HOLDER (C).
The Command holder (C) is a one-character static register that controls instruc-tion execuinstruc-tion. It is loaded with the six-bit command character of each instrucinstruc-tion word. An Instruction Error Interrupt request is generated if C does not provide an assigned command character. The content of the Command holder is displayed on the Central Processor Control Panel.
3.2.5 Z HOLDER (Z).
The Z holder is a one -character static register that controls command execution.
It is loaded with the Z character of each instruction word and is displayed on the Central Processor Control Panel.
3.2.6 Y HOLDER (Y).
Section III Paragraphs 3.2.6 to 3.2.9
The Y holder is a one -character static register that controls command execution.
It is loaded with the Y character of each instruction word and is displayed on the Central Processor Control Panel.
3.2.7 X COUNTER (X).
The X counter is a part of the phase control that participates in the execution of (character-serial) instructions. It is of interest after a Field Compare instruction, when it contains the number of comparisons completed, modulo 8, paragraph 4.3. 3.
The X Counter content can be transferred into the Core Memory by a Save ($) in-struction. It will appear as a decimal value, from 1 to 8, in the least significant character of the word in which it is stored, which otherwise is not altered.
3.2.8 INDEX MODIFY REGISTER (B).
The Index Modify register is a four -character static register that receive s the con-tent of the selected Index register prior to memory address modification or prior . to execution of a Modify Index Register instruction. The Index Modify register is not accessible to the program; however, it is displayed on the Central Processor Control Panel. The Index Modify register content does not change in response to Save, Load, or Copy instructions that specify an Index register.
3.2.9 INDEX REGISTERS (Xrl-XrI7).
The Central Processor is provided with a total of 17 Index registers, two of which are four -character static registers. The other 15 are the four least significant character positions of memory locations 00001 through 00015.
The Adder is used in a special mode to add the selected Index register content to the operand address of instructions. Index modification from a static Index regis-ter requires two extra clock times in addition to the time for the
instruction-procure memory cycle. Index modification from a memory index location requires two extra clock times in addition to the time for the Index-register-read memory cycle.
Index register content can be altered by the Modify Index register, paragraph 4. 5.6, Load, paragraph 4.2.6, and Copy, paragraph 4.2.8, instructions. Copy and Save instructions, paragraph 4.2.7, can transfer Index register content into another reg-ister or into Core Memory. Transfers are in four-character parallel.
Refer to paragraph 2.4.3 for a description of the indexing function.
Section III
Paragraphs 3. 2. 10 to 3. 3. 1
3.2.10 TOGGLES AND SWITCHES.
Addresses of all toggles, switches, and status tests are listed in Appendix C.
The ten Program Memo toggles can be individually or jointly tested, and can be set or reset under program control. The ON or OFF states of the toggles are in-dicated on the Central Processor Control Panel.
The nine individual Breakpoint switches on the Control Console, Section XIII, can be individually tested by program, but not altered.
For toggles used in MASM and PDPM modes, see paragraphs 3~ 4 and 3. 5.
For toggles involved in Search mode and the Compare instructions, see para-graph 4.3.
For a summary of Program Interrupts, see paragraph 1.10. For a detailed de-scription, refer to Section XI.