SET-RESET BIT

Command Character #

Section IV Paragraphs 4. 4. 2 to 4. 4. 3

Instruction #ZYXMMMM

x

(except X6) and MMMM not functional Options Tagged Halt, Flag Return

Mnemonic RBA, SBA, SSP, SSM

The decimal value of the numeric bits in the Z character of the instruction word specifies a character position in the A register (0 ~ Z ~ 7). The decimal value of the numeric bits in the Y character of the instruction word selects a bit within that character (1

S

Y ~ 6). (Z

>

7 or Y

>

6 gives no operation).

4.4.2.1 RESET BIT (Z5

=

0)-RBA, SSPo Reset bit ZY in the A register to

0.

The parity bit is automatically corrected, and no other bit position is modified. Continue with the next instruction in normal sequence.

4. 4. 2. 2 SET BIT (Z 5

=

I )-SBA, SSM. Set bit Z Y in the A register to 1. The parity bit is automatically corrected, and no other bit position is modified. Continue with the next instruction in normal sequence.

4. 4. 3 LOGICAL OR.

Command Character V

Instruction VZYXMMMM

x

(except X6) and MMMM not functional Options Tagged Halt, Flag Return

Mnemonic OR

The decimal value of the numeric bits in both the Z character and the Y character of the instruction word each specify a character position in the A register; 0~(Z and Y)

~ 7. (Z or Y

2::

8 leads to no operation. )

Logically OR each numeric and zone bit contained in the Z character position of the A register with the corresponding bit in the Y character position of the A register.

The OR operation produces a 1 bit if there is a I in either the Z or Y specified cor-responding bit positions, and provides a 0 if there is not. Place the result bit-by-bit in the Y character position. The parity bit is automatically corrected, and no other bit position is modified. Continue with the next instruction in normal sequence.

Section IV

Paragraphs 4. 4. 4 to 4. 4. 5. 2

4. 4.4 LOGICAL AND.

Command Character 1\

Instruction 1\ ZYXMMMM X (except X6) and MMMM not functional Options Tagged Halt, Flag Return

Mnemonic AND

The decimal value of the numeric bits in both the Z character and the Y character of the instruction word each specify a character position in the A register;

0:s(Z and Y):S7. (Z or Y~8 leads to no operation.)

Logically AND each numeric and zone bit contained in the Z character position with the corresponding bit in the Y character position of the A register. The AND oper-ation produces a 1 bit if there is a 1 in both the Z and Y specified corresponding bit positions, and provides a 0 if there is not. Place the result bit-by-bit in the Y character position. The parity bit is automatically corrected, and no other bit position is modified. Continue with the next instruction in normal sequence.

4. 4. 5 CONVERT.

Command Character P

Instruction PZYXMMMM Z, Y, X, (except Z6, Y6, X6) and MMMM not functional

Options Tagged Halt, Flag Return

Mnemonics CBD, CDB

4. 4. 5. 1 BINARY TO DECIMAL (Y6

=

1) - C BD,. Convert the binary value of bits 1-6 of character C3 in the A register to a two digit decimal equivalent. Store the most significant digit in the numeric bits of character C4, retain the least signifi-cant digit in character C3, and reset the zone bits of both character positions to 0.

No other character position in the A register is modified, and the content of the R register is unchanged.

4. 4. 5. 2 DECIMAL TO BINARY (Y6

=

1) - CDB. Convert the two digit decimal num-ber retained in the numeric bits of character C4 (most significant) and character C3 (least significant) in the A register to an equivalent binary number. Store the result in bits 1-6 of character C3, and reset bits 1-6 of character C4 to 0. No other charac-ter position in the A regischarac-ter is modified, and the content of the R regischarac-ter is

Section IV Paragraph 4. 5 unchanged. A converted binary value greater than

63

will set ON the Convert Over-flow Error Interrupt toggle (Z Y

=

^{W 4).}

4. 5 PROGRAM CONTROL INSTRUCTIONS.

The seven program control instructions specify conditional or unconditional program skip, jump, and halt operations. Unless otherwise specified, the program will con-tinue with the new instruction sequence after a jump in program control.

The No Operation instruction (N) advances the program to the next instruction in normal sequence, without executing any operation. It can be useful in deleting an instruction used only during program debugging. The Unconditional Transfer in-struction (U) jumps the program to the designated memory address, and uncondi-tionally initiates a new instruction sequence. The Nand U instructions also may be utilized in conjunction as a simple means of providing switching points within the program. The branches are set to one of two positions by inserting either the N or U order code into the command character position of the instruction word.

The Test instruction (T) checks for the specified True or False status of the Z Y designated line, switch, or toggle. If the stated condition is met, the program jumps to the effective memory address. The program testable toggles and lines are listed in Appendix Co

The Bit Compare instruction (~:~) tests for the specified 1 or '/J status of the Z Y se-lected bit in the A register, and jumps the program to the effective operand address if the stated condition is met. Also, it may compare for equality or complete non-equality between the Y selected bits of the Z designated character in the A register and the corresponding bits in the effective operand address. The Bit Compare in-struction facilitates the checking of individual or combinations of flags and switches.

The Execute instruction (X) provides execution of a single designated instruction, with unconditional or optional return to the initial program sequence. This capa-bility is useful in program debugging, by permitting the step-by- step execution and monitoring of individual instructions.

The Modify Index Register instruction ( 0) will algebraically modify the absolute content of the Z selected Index register by Y, where

-9

~ Y ~

+9.

This instruction automatically provides proper binary-decimal address modification, and the zone bits in the three least significant character positions of the Index register are ignored. The program continues with the next instruction in normal sequence if index modification exceeds core memory addressing capacity

(0-63, 999);

otherwise

Section IV

Paragraphs 4. 5. 1 to 4. 5. 3. 1

the progralTI jUlTIPS to the designated lTIelTIory address. The MOdify Index Register instruction, in conjunction with the indexing option, facilitates the repetitive use of progralTI instructions and routines.

The Halt instruction (Z) provides either an unconditional progralTI halt, or a condi-tional halt dependent on the Z Y addressed Breakpoint button on the Control Console being in the ON position. Depressing the Start or Step button on the Control Console, following a halt, jUlTIPS the progralTI to the effective lTIelTIory addres s. The Z

in-struction increases debugging flexibility by perlTIitting optional halts and checks at specific points in the progralTI.

4. 5. 1 NO OPERATION.

COlTIlTIand Character N Instruction

Options MnelTIonic

NZYXMMMM Z, Y, X (except z6 and X6) and MMMM not functional

Tagged Halt, Flag Return NOP

No operation; continue with the next instruction in norlTIal sequence.

4. 5. 2 UNCONDITIONAL TRANSFERo COlTIlTIand Character U

Instruction UZYXMMMM Z (except Z6) and Y not functional Options Index, Indirect-Address, Tagged Halt, Flag Return

MnelTIonic JUMP

Unconditionally access the next instruction at the effective operand address M.

4. 5.3 TEST.

COlTIlTIand Character T

Instruction TZYXMMMM

Options Index, Indirect-Address, Tagged Halt, Flag Return

MnelTIonic TIOF, TION

405.3. 1 TRANSFER IF FALSE (Y6

=

^{0) -} TIOF. Access the next instruction at the effective lTIelTIory address if the ZY addressed toggle or line is false; otherwise con-tinue with the next instruction in norlTIal sequence.

Section IV Paragraphs 4. 5. 3. 2 to 4. 5. 4.·2 4. 5. 3. 2 TRANSFER IF TRUE (Y6 = 1) - TION. Access the next instruction at the effective memory address if the Z Y addres sed toggle or line is true; otherwise con-tinue with the next instruction in normal sequence.

Refer to paragraph

6. 9

for the use of the Test instruction in the 110 Interface.

Refer to paragraph 7. 8. 3 for the use of the Test instruction in the Uni-Record Interface.

The list of Z Y addres sable toggles and lines is given in Appendix C.

Use of an unassigned ZY address gives an undefined result.

4. 5. 4 BIT COMPARE.

Command Character

Instruction ^~(ZYXMMMM

Options Index, Indirect-Address, Tagged Halt, Flag Return .

Mnemonic TBAT, TCHM

4. 5. 4. 1 TEST BIT (Z5

= t» -

TBAT. The decimal value of the numeric bits in the Z character of the instruction word specifies a character position in the A register

(t> S z

~ 7). The decimal value of the numeric bits in the Y character of the instruc-tion word selects a bit within that character (1 ~ Y ~ 6). (Other values of Z and Y lead to undefined results. )

Te st bit Z Y in the A register. Acce s s the next instruction at the effective operand address M if the bit is equal to 1; otherwise continue with the next instruction in normal sequence.

4.5.4.2 TEST (COMPARE) CHARACTER (Z5

=

1) - TCHM. The decimal value of the numeric bits in the Z character of the instruction word specifies a character position in both the A register and in M

(t> S

Z

.$

7). The numeric and zone bits in the Y character of the instruction word control the bit- by-bit comparison between the content of the Z selected character positions. The comparison toggles Equal and the Equal to Complement toggle (ZY

=

58) are reset OFF automatically prior to instruction execution.

Each numeric and zone bit contained in the Z character position of the A register is compared with the corresponding bit position in memory address M when the equiva-lent bit position of the Y character in the instruction word is a 1. Those bit positions where the Y character contains a

t>

are ignored. The Compare EQ toggle is set ON

Section IV

Paragraphs 4. 5. 5 to 4. 5. 6

if all the Y

=

1 specified bits in the Z character position of the A register and of M are equal. The Equal to Complement toggle is set ON if all the specified bits are unequal. Any other condition will not modify the status of any toggle unless all bits of the Y character are

0'

s in which case both the Equal and Equal to Complement toggles are set ON.

The program continues with the next instruction in normal sequence.

4. 5. 5 EXECUTE.

Command Character

x

Instruction XZYXMMMM

Options Index, Indirect-Address, Tagged Halt, Flag Return, PDPM

Mnemonic XECR, XECA

4. 5. 5. 1 UNCONDITIONAL RETURN (Z 5

=

^{0) - XECR.} Execute the instruction located at the effective operand address M. Return to the instruction following the Execute instruction.

4. 5. 5. 2 CONDITIONAL RETURN (Z 5

=

1) - XECA. Execute the instruction located at the effective operand addre§§ M. Return to the instruction following the Execute instruction unless the instruction at M produces a program jump (conditionally or unconditionally). If such a jump is specified, transfer program control to the jump address and continue with the new instruction sequence.

4. 5. 5.3 REMARKS. An Executed instruction does not have the MASM Instruction Modify (bits 15 and 16) and Flag Return (Z6) options. After fetch of the executed instruction, the sequence of operations leading to instruction execution is re- entered at point @ of paragraph 3. 3. 3.

4. 5. 6 MODIFY INDEX REGISTER.

Command Character

o

Instruction OZYXMMMM

Options Index, Indirect-Address, Tagged Halt, Flag Return

Mnemonic TXD, TXI

The numeric bits and the sign bit of the Y character in the instruction word specify an algebraic decimal value of -9~ Y ~ 9. A Y6

=

1 designates a minus sign and a y6

= 0

provides a plus sign. Bits 1 ... 5 of the Z character in the instruction word

Section IV Paragraphs 4. 5. 7 to 4. 6 provide a binary value to select index registers XR 1 through XR 17. (A value of

.

Y

>

9 in magnitude is treated as a zero. )

The absolute content of Index register Z is modified by the algebraic value of Y.

The program continues with the next instruction in normal sequence if the result exceeds Core Memory capacity (less than '/J'/J'/J'/J or greater than 63, 999); otherwise, the program accesses the next instruction at the effective operand address. If no Index register is selected by the Z character (binary value not in the range 1 to 1 7), the

0

instruction terminate s after completing all specified program control options.

4. 5. 7 HALT.

Command Character Z

Instruction ZZYXMMMM

Options Index, Indirect-Address, Tagged Halt, Flag Return

Mnemonic BPHTR, HTR

4. 5.70 1 UNCONDITIONAL HALT - HTR. An unconditional halt is specified if the Zy characters in the instruction word are 5[. Depressing the Start or Step button on the Control Console, after a Halt, causes the next instruction to be accessed at the effective operand address.

4.5.7.2 CONDITIONAL HALT - BPHTR. There are 9 Breakpoint buttons in the Control Console. They are labelled 1, 2, 3, 4, 5, 6, 7, 8, 9 and have Z Y address of 5/, 5S, 5T, 5U, 5V, 5W, 5X, 5Y, 5Z, respectively. A Halt is specified if the Breakpoint button addressed by the Z Y characters of the instruction word has been depressed and is in the ON position. Depressing the Start or Step button on the Control Console, after a Halt, causes the next instruction to be accessed at the effective operand addres s M.

The Central Processor continues with the next instruction in normal sequence if no Halt is specified. Other ZY addresses give no operation.

Im Dokument General Precision, (Seite 88-94)