While a variety of fault models exist [Wun10], the structural stuck-at-fault model and the transition delay fault model will be depicted in the following.
2.3.1.1. Stuck-At Fault Model
The most widely used fault model is the stuck-at fault model [Eld59; GNR61]. It assumes, that astuck-at fault (SAF)affects a single line or signal of a circuit, where the faulty line is permanently set to either logic 0 At-0 or SA0) or logic 1 (Stuck-At-1 or SA1). A large variety of defects can be represented with this simple model, although it cannot model defects that involve multiple signals or time-dependent defects.
Definition 2.3.1 (Stuck-At Fault) A stuck-at fault saf in a combinational circuit C = (V,E) is a pair saf ∈ E × B, where the first component denotes the fault location and the second component denotes its polarity.
2.3.1.2. Transition Delay Fault Model
The transition fault model supposes, that a single gate in a circuit exhibits a delay increase over its nominal value. The delay of the faulty gate is assumed to be suffi-ciently large to prevent a passing transition from reaching any output within the circuits clock period, independent of the path involved. Thus, transition faults are also called gross-delay faults and either affect the 0 →1 transition (Slow-To-Rise, STR) or the 1 →0 transition (Slow-To-Fall, STF) of a gate, usually defined with respect to the transition of the gate output.
Definition 2.3.2 (Transition Fault) A transition fault tf in a combinational circuit C = (V,E)with gatesGC ⊂ V is a pair tf ∈ GC×{STR,STF}, where the first component denotes the affected gate and the second component denotes the polarity of the output transition exhibiting a delay greater than the system clock.
2.3. Test of Digital Circuits
2.3.2. Test Access through Scan Design
During test, input stimuli are applied to a circuit and the circuits answer is compared to the expected test response. For combinational circuits this is achieved by controlling the (primary) inputs and observing the outputs. In sequential circuits, where an internal state is stored in latches or flip-flops, the testability of these sequential elements is crucial.Scan designprovides direct controllability and observability of the sequential elements [WA73; EW77]. The original sequential elements are replaced by scannable implementations, that are connected serially in order to form a shift register, called ascan chain.
Inedge-triggered designswhere a single clock is used to control the sequential circuit part, a scannable register can be implemented by multiplexed flip-flops as depicted in Figure 2.4. The test control signalScanEnableis used to select if the flip-flop’s inputs are connected to the combinational circuit insystem mode, or to the outputs of the predecessing flip-flops intest mode.
ScanIn FF CLKScanEnable
ScanOut
FF
…
FF0 1
0 1
0 1
Figure 2.4.: Multiplexer-based Scannable Register (adopted from [BA00]).
In level-sensitive designs, that are considered especially robust against timing varia-tions,level sensitive scan design (LSSD) is used [EW77]. TheL1/L2shift register latch (SRL)depicted in Figure 2.5-a is controlled by one system clock and two test clocks Aand B. In system mode, theL1latch is used to store data from the combinational circuit controlled by clockClk. In test mode, the inputScanInis controlled by the two non-overlapping clock signalsA,B. Hence, theL2 latch is only used to implement the shift mode. Also in system mode, latches have to be controlled by a non-overlapping clock scheme. The simplest scheme is shown in Figure 2.6. The timesτ1l andτ1h are the low resp. high phases ofclk1,τ2l andτ2h are these phases ofclk2, andclk1 andclk2
are never high at the same time. As these latches are available anyway they can be combined to so calledL1/L2∗ latches to implement a single SRL (Figure 2.5-b), where theL2 latch is no longer redundant.
ScanIn L1 Clk L2
A B ScanOut ScanIn L1
Clk1 L2*
A ClkB2 ScanOut
a) L1/L2 b) L1/L2*
Figure 2.5.: Shift Register Latch.
clk1
clk2
τ1l τ1h
τ2l τ2h
Comb.
Circuit
Comb.
Circuit
Register A Register B
clk1 clk2
Figure 2.6.: Non-overlapping Clock Scheme.
An overview on the vast amount of different scan architectures targeting different design styles is found in [BA00].
Hence, in presence of scan design, arbitrary combinational test patterns can be applied as a sequential circuitC withnprimary inputs (PI),mprimary outputs (PO) and k sequential elements behaves like a combinational circuitCC withn+k inputs and m+k outputs. The additional k in- and outputs are calledpseudo primary in- and outputs (PPI and PPO). Test application of such a test set is conducted as follows. Each test pattern pi consists of two parts, a sequential statesi and an assignment of the primary circuit inputsvi. The expected response of a pattern similarly contains values of the primary outputsoi and a sequential state s′i. The sequential state si is shifted serially into the scan chain(s), thereby guaranteeing that the scannable sequential elements are in the desired state. Then, the inputs vi are assigned and the circuit is operated in normal mode for one clock cycle during the capture cycle. Afterwards, the circuit outputs are compared to the expected valuesoi and the sequential state is shifted out and compared to s′i. At the same time, the sequential state si+1 of the next pattern is shifted in.
The time to apply a set of test patterns is called the test application time (TAT)ortest time, which is dominated by the shift operations of the scan chains. Thetest data
2.3. Test of Digital Circuits
volume (TDV) ortest volumedenotes all bits exchanged with the circuit during test.
During test application, the peak and averagetest power consumptionas well as the test energy are elevated due to the shift operations causing a high switching activity in the scan chains as well as the combinational circuit [IZW+07; EWI+08].
2.3.3. Test Algorithms
2.3.3.1. Fault Simulation
Fault simulationdenotes the process of simulating a set of test patternT for a circuit C in presence of faults from a fault set F. For every input stimulus t ∈ T, a logic simulation of thefault free circuit, thegood value simulation, is conducted to determine the fault free circuit response. Then, the circuit model is modified duringfault injection in order to represent the presence of a fault f ∈ F and the resulting faulty circuit is simulated. If the test response of the good and faulty circuit differ,t is said to be a test for fault f as fault f is controlled and observed under testt.
Typically, the number of test patterns inT and the number of faults in F that need to be considered are large. Fault simulation can be accelerated by fault dropping, where faults that have already been detected by previous patterns are removed from the fault list. Orparallel-pattern single-fault propagation (PPSFP)is employed, where multiple patterns are evaluated concurrently during the simulation of a single fault [WEF+85].
During fault simulation of a test setT, the faults of a fault setF are distinguished intodetected andundetectedfaults, where F = Fdetected∪Fundetected. This classification is used as a metric for the quality of a test setT, thefault coverage.
Definition 2.3.3 (Fault Coverage) Given a circuitC, a set of faultsF and a test set T, then the fault coverage FC(T) is defined as
FC(T) := |Fdetected|
|F| × 100 % .
A perfect fault coverage cannot always be reached as some of the faults in a circuit are undetectable(F = Fundetectable∪Fdetectable with Fdetectable = Fdetected ∪Fundetected ).
Hence, theeffective fault coverageorfault efficiency is used as a metric, where 100 % denote the maximum quality that a test set can reach.
Definition 2.3.4 (Fault Efficiency) Given a circuit C, a set of faults F, a set of proven undetectable faults Fundetectable ⊂ F and a test set T, then the fault efficiency FE(T) is defined as
FE(T) := |Fdetected|
|F| − |Fundetectable| × 100 % .
2.3.3.2. Test Pattern Generation
In case of an insufficient test coverage, additional test patterns are required to target yet undetected faults. The process of generating test patterns that show the presence of faults in a circuit is called Automatic Test Pattern Generation (ATPG), which is known to be a NP-complete problem [IS75]. A brief introduction to test generation is given here, while more details are provided in literature [BA00].
The ATPG process needs to fulfill two conditions to generate a test for a targeted fault:
Fault activationandfault propagation. For stuck-at faults, fault activation requires that the fault location is excited to the opposite logic value of the fault polarity, that is 0 for a SA1 and 1 for a SA0. Fault propagation requires that a sensitized path from the fault location to a primary output exists, over which the fault effect can be observed.
For transition faults, pattern pairs P = (p1,p2) are required, where theinitialization pattern p1excites the fault location to the initial value of the targeted transition (0 for STR and 1 for STF). Thepropagation pattern p2excites the fault location to the final value of the targeted transition (1 for STR and 0 for STF), and sensitizes a path from the fault location to a primary output.
Test generation can be conducted by traversing the structural circuit description in structural ATPG, or can be formulated as a Boolean satisfiability problem (SAT) [DEFT09; Czu13]. To satisfy a fault’s activation and propagation condition, the input assignment of the test pattern needs to guarantee the required values of circuit signal lines. Typically, thisline justificationonly needs to specify a small amount of input bits to derive a test pattern for a single fault. The specified bits of a test pattern are calledcare bits, whereas the unspecified bits are denoted asdon’t carebits. Specifying the don’t care bits of a partially specified pattern allows the detection of additional faults, which can be determined by fault simulation of the filled pattern. Limiting the maximum number of specified bits increases the efficiency of test compression and compaction in reducing the test time and volume [KZIW08].