Many different lossless compression techniques exist for the input vectors, which rely on one of the following three basic principles [Tou06]:
▷ Applying the same value to multiple scan chains in broadcast-scan-based schemes,
▷ data compression codes used incode-based schemes, or
▷ linear operations implemented as exclusive-OR networks or LFSRs in linear-decompression-based schemes.
Compressed ATE
Stimuli
Compacted Responses
Decompressor Compactor
Figure 3.5.: General Embedded Deterministic Test (EDT) Architecture (adopted from [RTK+02]).
The lossy compaction of test responses at the output side is either performed in the time or space domain:
▷ Time compactionor infinite-memory compaction employs linear finite state machines, such as linear feedback shift registers (LFSR) or multiple input shift registers (MISR). The test responses are compacted into a small signature and high compaction ratios are reached. Unknown values1in the test responses corrupt the signature and render the test useless.
1An unknown state of signals during the design process, e.g. due to incompletely specified models, which is indeterminable during test generation/simulation but a valid binary value during test.
3.2. Test Access
▷ Space compaction uses combinational circuits built of exclusive-OR gates to reduce the amount of required outputs. The reachable compaction ratios are lower as compared to time compaction, whereas unknown values in the test responses can be handled.
▷ Convolutional compactionor finite-memory compaction combines space com-paction with a finite memory without feedback.
The embedded deterministic test architecture in [RTK+02; RTKM04] uses a sequential linear decompressor, that is dynamically reseeded by injecting a fixed amount of free variables shifted in from the tester during decompression. In combination with a linear spatial compactor, test data volume is reduced by up to 25 X. If the convolutional compaction from [RTWR03; RTWR05] is used at the output side, compression ratios in excess of 100 X can be reached as long as the decompressor is considered during test generation and the test responses contain a low amount of unknown values.
The X-compact scheme in [MK02; MK04] focuses on the response compaction by combinational circuits in presence of unknown (X) values. In combination with a linear decompressor at the input side, arbitrary deterministic patterns can be applied [MK03; MK06].
3.2.2. Random Access Scan
An alternative architecture to increase testability is calledrandom-access scan (RAS) [And80]. It allows to address individual flip-flops during test mode similar to the access provided in random access memory (RAM) blocks. Therefore, a general RAS architecture organizes the flip-flops in a two-dimensional array (Figure 3.6).
During functional mode (TC=0) all flip-flops latch data from the combinational logic under the control of the clockCLK and the flip-flop outputs feed into the combina-tional logic. A typical storage element used in the addressable array, called aRAS cell, is given in Figure 3.7.
During test mode (TC=1) individual flip-flops can be read and written. To select a flip-flop, its x- and y-addresses are serially loaded into the twoaddress shift registers (ASR) with an additional clock ACLK. For a total amount of n × m bits organized intoncolumns andmrows, the address sizes are ⌈log2n⌉ respectively ⌈log2m⌉. The address decoders enable the x- and y-select signals for the addressed flip-flop, while all other select signals stay 0. As only single flip-flops can be addressed, the scanout
Combinational Circuit Cc
…
…
CLKTC SDI
SDO
x Address Shi Register (x-ASR)
y-ASR
Addressable array of RAS cells n x m bits
(log2n bits) (log2m bits)
y-ADR x-ADRACLK
x Address Decoder
y Address Decoder
Figure 3.6.: General Random Access Scan Architecture.
signalsSO of all RAS cells are tied together to the global scanout pinSDO. As soon as a RAS cell is selected, its value is observable at the SDO output (independent of the value of the mode signal TC). To write a cell during test mode (TC=1), the x- and y-select signals of the addressed flip-flop are 1, and the value ofSI is latched in the flip-flop byCLK. All scanin inputsSI of flip-flops are connected to the global scanin pinSDI. As the select signals of not addressed flip-flops are not conjointly 1, the clock signalCLK is blocked and SDI is not latched in other flip-flops.
RAS is able to reduce the test time associated with controlling and observing the flip-flop states, but incorporates a large overhead [BA00]. The address decoders and shift registers require additional gates and thereby area. In addition to the clock and select signals, three signals need to be connected to every RAS cell: TC, SDI, SDO. Thereby, significant routing effort and interconnect resources might be required as the RAS cells are distributed within the circuit layout to minimize the impact on circuit delay during functional mode. Moreover, each RAS cell itself incorporates additional gates compared to the scan cells used in scan design. While the RAS architecture has been used in practice [Ito90], it did not gain popularity, perhaps due to the large overhead involved [BA00]. A series of publications built upon the basic RAS idea in order to reduce the overhead and improve the test time, volume, and power.
3.2. Test Access
FF 0
1 CLKTC
x select
y select & &
D Q
SO SI
0 1
Figure 3.7.: Multiplexer-based Addressable Random Access Scan Cell.
InProgressive Random Access Scan (PRAS)[BS05a], the RAS cell consists of a trans-mission-gate based flip-flop, where the master latch is extended by two additional transistors. Thereby, a SRAM cell is formed which is accessed over sense lines as in a regular SRAM. Read operations are performed in parallel for complete rows and compacted into a signature with the help of a MISR implemented together with the sense amplifiers. While reducing the area of the RAS cell, additional overhead arises from the doubled amount of column select lines (positive and negative polarity), the column drivers and the sense amplifiers.
The idea behind Toggle RAS is to invert the value stored in a RAS cell instead of writing it [MAS05a; MAS05b]. The inversion is implemented by a toggle-flip-flop that is activated whenever a cell is addressed in order to be read. Thereby, the global SDI network driving the SI inputs of all cells is eliminated. The combination of toggle RAS and progressive RAS depicted in [AAS+10] further reduces the hardware overhead by modifying the T-FF based RAS cells. For reading, a combination of sense amplifiers with a MISR is utilized similar to progressive RAS, thereby allowing to read and compact complete rows.
In principle any test set can be applied using Random Access Scan, although it might result in elevated test time and test volume. In RAS, the test time depends on the amount of write and read operations required during test application, whereas the time to conduct each operation is dominated by the required shifts of the address registers. The number of write operations between two test vectors is equal to the Hamming distance between the sequential states of the vectors.
In [BSK04; BS05a] existing test sets are reordered to minimize the amount of address scan operations needed during test application in the RAS architecture. The problem is modeled as a asymmetric traveling salesman problem, where the Hamming distance
between test vectors serves as a cost function. The heuristically determined solution is further improved by identifying don’t care values in the test vectors and appropriate filling (before and after the reordering). If multiple bits differ between vectors, the write operations are reordered to minimize address shifts by reusing portions of the scanned addresses. [BSK04] compares the reordered test sets for benchmark circuits equipped with a single chain for serial scan and a single address register for RAS. The reordered test sets show a test time speedup between 1.06 X and 5.3 X, a test volume reduction by between 25.27 % and 82.26 % and a test power (defined by the number of gate outputs switching) of below 1 % compared to serial scan. In [BS05a] the reordered test sets are evaluated w.r.t. multiple (3 to 4) scan chains. A speedup between 1.9 X and 4.6 X and a volume reduction between 10.4 % and 62.6 % are reported.
In [BS05b], a test generation procedure for Progressive RAS is described. It iteratively generates test patterns, where each test pattern targets the faults with the highest probability of being detected by the current state of the RAS cells. Thereby, every generated test pattern has a low Hamming distance to the current state. In comparison to the test set reordering in [BS05a], the test time and volume are reduced by additional 20 % on average, with a maximum reduction by up to 50 % for two circuits.