Chapter 2
Formal Foundation
This chapter defines the formal apparatus used throughout this work. First, definitions for combinational and sequential circuits are depicted along with the nomenclature used to describe deviations from the intended design and erratic behavior at different abstraction levels. In the following, the fundamentals of soft errors are described in terms of the used nomenclature, their quantification, and fault tolerance by means of redundancy. In the test domain, the essential fault models are discussed in combination with design for testability by test infrastructure and elementary test algorithms. At last, Boolean satisfiability is introduced as a foundation for Chapter 7.
The Y-chart proposed by Gajski and Kuhn and later refined by Walker and Thomas [GK83; WT85] is commonly used to distinguish five abstraction levels that comprise details from three domains of description: The behavioral, the structural and the physical domain. During the top-down design process a higher level description of a design is refined and transformed into a lower level description. Starting from the design specification at the architectural or system level, the algorithmic level describes the function of a circuit in ahardware description language (HDL)without any assumptions on the implementation or internal organization. Thefunctional block or register transfer level (RTL)adds structural information by distinguishing sequential and combinational logic. Individual registers are modeled together with constructs familiar from programming languages describing the data and control flow. Alogical (gate) level implementation is then synthesized from the RTL description. Thisgate level netlist models a circuit as a set of components and a set of signals connecting them. Each component is a (logic) gate and implements a Boolean function. Similar to the composition of functional blocks from gates and connections between them, at thecircuit (transistor) level individual gates are described in the structural domain as netlists that contain transistors, resistors and capacitances. On the contrary, in the physical domain the actual layout and routing information of individual gates is modeled by the geometric description of the masks used for production.
Throughout this work logic level modeling is assumed due to the following reasons.
The abstraction level of a gate netlist provides structural information by modeling single gates and their interconnect, which is necessary to model structural faults, perform fault simulation and to reason about test pattern generation. A logic level gate netlist is also technology-independent. Gates, as the smallest units, are defined by their input and output vectors as well as their Boolean function independent of their physical implementation. If a model at the circuit level is mandatory to assess the area overhead or determine the probability of radiation induced soft errors, a gate netlist can be easily mapped to any technology that provides a (technology-dependent) standard cell library.
2.1.2. Combinational Circuit
A digitalcombinational circuit CC is a device with ninputs and m outputs imple-menting a Boolean function φCC :Bn →Bm. In Figure 2.1, the gateg2 is called a predecessor ofg4, whileg6 is asuccessor ofg4. More general, for any circuit element
2.1. Digital Circuits
Support Output
Input Cone Cone
g2
g6
Inputs Outputs
i1 i2
i5
o1
o2 i3
i4
g1
g3
g4
g5
Figure 2.1.: Combinational CircuitCC.
ethe terminput cone ofe denotes the subcircuit containing all predecessors ofe, and theoutput coneof econsists of all its successors. The subcircuit denoted as the support ofecontains all input cones of the outputs that are successors ofe.
At the gate level the combinational circuitCC is represented by a directed acyclic graph (Figure 2.2) which is called a gate level netlist and defined as follows.
Definition 2.1.1 (Combinational Gate Level Circuit) A combinational gate level circuit CC is a directed acyclic graph with vertices V and edges E ⊂ V × V. V := I ∪GC ∪O∪F is a disjoint union of the input vertices I, combinational verticesGC and output verticesO as well as fanout vertices F.
i1 i2 i3 i4 i5
o1
o2 g1
f1
g2 f2
g4
g3 f3
g5
g6
Figure 2.2.: Graph ofCC. The edges represent connections between nodes called
nets, wiresorsignals. The number of connections of a vertex depends on its type. Input vertices have only outgoing edges, while output vertices have exactly one incoming edge.Fanout verticeswith exactly one incom-ing edge, the fanout stem, and at least two outgoing edges, calledfanout branches, are used to connect mul-tiple signals. The remaining vertices represent combi-national logic gates. Each logic gate g ∈ GC with l inputs and one output implements a Boolean function φg :Bl →Bdefined by the gate type.
Throughout this work, logic gates with a maximum of two inputs are assumed, as gates with more inputs can be built from two-input gates.
2.1.3. Sequential Circuit
A sequential circuit is a circuit whose output function does not solely depend on the values present at its inputs, but on their history (Figure 2.3). This sequential state is represented by storage elements, such as latches and flip-flops, which are controlled by a clock signal insynchronous sequential designs. Two design styles can be distinguished dependent on the sensitivity to the clock signal. Inlevel-sensitive designslatches are used, that are transparent whenever the clock signal has a certain logic value (0 or 1) and latch data by retaining their state during the opposite value of the clock signal. Inedge-triggered designsthat employ flip-flops, new data is latched at a specific clock transition (rising or falling) and stored otherwise.
Asequential circuitC withninputs,m outputs andk sequential elements is afinite state machine (FSM) [Mea55]. The up to 2k states are encoded by the data stored in the sequential elements. Thecombinational coreCC computes two Boolean functions.
Theoutput function φC : Bn × Bk → Bm, that maps pairs of an input and a state to an output and the transition functionτC : Bn × Bk → Bk, that maps pairs of an input and a state to the next state. Typically, collections of sequential elements that are accessed together are grouped intoregistersas depicted in Figure 2.3.
2.1.4. Defect, Fault, Error, Failure
This work distinguishes incorrectnesses in digital circuits at different abstractions in accordance to Bushnell and Agrawal [BA00]. At the physical level, the termdefect is used to describe distortions of the physical shapes in a circuit layout arising from the manufacturing process or during the operation of devices.
Definition 2.1.2 (Defect [BA00]) A defect in an electronic system is the unintended difference between the implemented hardware and its intended design.
Afaultis a formal representation of a defect, that abstracts the physical properties of the infinite and non-discrete range of defects.
Definition 2.1.3 (Fault [BA00]) A representation of a “defect” at the abstracted func-tion level is called a fault.
2.1. Digital Circuits
Inputs Combinational Circuit CC
Register R1
Register Ri
Sequential State
m n
k
k
Outputs
Figure 2.3.: Sequential CircuitC.
If the fault is activated and thus visible at the information theoretical view, it is called an error.
Definition 2.1.4 (Error [BA00]) A wrong output signal produced by a defective sys-tem is called an error. An error is an “effect” whose cause is some “defect”.
If an error becomes visible at the system boundary and results in a loss of the intended system function, it is called afailure.
Definition 2.1.5 (Failure [Muk08]) Failure is defined as a system malfunction that causes the system to not meet its correctness, performance, or other guarantees.
Example Suppose a signal in a circuit that is shorted to the supply voltage signal due to an impurity introduced during the manufacturing process. This defect can be modeled as a fault by the assumption that the signal always has a logic value of 1. It is activated whenever the driving gate produces a logic 0 and manifests as an error as the signal has a logic value of 1 instead of 0. If the error results in a wrong calculation of the circuit, the system fails.
The causes of failure fall into three broad categories [Con03].Permanent faultsexhibit a behavior that does not change with time at a fixed location. They are also called hard faultsand can be attributed to physical defects. In contrast,non-permanent faults occur randomly and can be further subdivided by their location.Intermittent faults
appear and disappear as a function of time at a fixed location. They relate to marginal or unstable hardware, are activated by environmental conditions, and may evolve into permanent faults. Transient faultsaffect a circuit at random timepoints and random locations. They are caused by environmental conditions such as dynamic parameter variations that lead to violations of timing safety margins [Con03; Bor05] or the charge induced by ionizing radiation [Bau05]. Thus, they are often more precisely denoted astransient errorsto accentuate the absence of a physical defect orsoft errors for particle-induced transients.