Test since ever is an essential task in the production process of digital circuits. Test is an experiment to prove the presence of hard faults arising from the production process and is used to assess the quality of delivered ICs. This section depicts the basic concepts and the challenges associated with testing, whereas the book of Bushnell and Agrawal provides a more detailed discussion [BA00].
Functional testing describes the most obvious form of testing. A digital circuit imple-menting a Boolean function is provided with input assignments in order to exercise the specified functionality of the circuit. For each input assignment, the correct an-swer of the circuit is known according to the implemented function. The combination of an input assignment and the intended answer is called a test pattern, whereas the aggregation of multiple patterns is called a test set. The circuits response, the test response, is then compared to the expected answer. If a match is found, the test pattern is said to pass, otherwise, the patternfailed. Functional testing only accounts for the specified behavior of a circuit and does not consider the implementation. Due to the high number of implemented functions and possible input values some defects might not be detected by functional testing, which are described astest escapes. Coverage of a circuit can only be defined according to the tested functionalities (for selected values) and no assertion can be made with respect to the coverage of structural defects.
Structural testing is independent of the implemented functionality and exercises the structural implementation of a circuit. The behavior of defects is abstracted with the help of afault model, with afaultbeing specified by its behavior and the affectedfault location(usually signals or gates). In the most commonly usedstuck-at fault model, faults can occur at circuit signals, whereas a signal can be either stuck-at-0 (SA0)or stuck-at-1 (SA1). A procedure calledAutomatic Test Pattern Generation (ATPG)is used to generate a test set covering all faults contained in the fault set.
Testing can be conducted asexternal test, where test sets are applied to the circuit with the help ofAutomatic Test Equipment (ATE), also calledtester. Or the test patterns are generated on-chip by additional circuitry duringBuilt-In Self Test (BIST). Testing is typically performed in the fab between different production steps and prior to delivery of ICs, which is calledmanufacturing test, or, with the help of BIST infrastructure as an in-field test, e.g. during power-up of safety critical devices such as cars.
1.2. Test and Design for Test
1.2.1. Testability and Test Infrastructure
Testability is the primary metric used in test. In order to detect a fault, the according test pattern needs to excite the fault location to a desired value, but some locations are harder to excite than others due to the circuit structure or the presence of sequential elements.Controllabilityis defined as the difficulty to drive a signal to a desired logic value [Rut72]. In addition, the logic value of the fault site must be propagated to a circuit output in order to determine if the test pattern passed or failed.Observability is defined as the difficulty to observe the logic value of a signal [Gol79]. The first testability metric inheriting both aspects is the ‘Scandia Controllability/Observability Analysis Program’ [GT80].
Testability can be increased bydesign for test and the introduction oftest infrastruc-ture.Scan design[EW77] is the most widely used test infrastructure to increase the controllability and observability of sequential elements. Ascan chain is a register composed out of latches or flip-flops. In addition to the parallel access provided to the circuit, it implements an additional test mode during which the scan-chain behaves like a shift-register. The register values can then be read and written over two additional signals in a serial way by bitwise shifting the chain. If all sequential elements of a circuit are added to scan-chains, the circuit is said to be equipped with full scan. Although the introduction of scan design is able to significantly increase testability, it incorporates additional area overhead, additional pins fortest accessand increasedtest timeas well asswitching activity for the necessary shift operations.
During test application, the test patterns have to be provided to thecircuit under test (CUT)and the test responses have to be fetched and checked. The amount of all data exchanged by the ATE and the CUT is denoted by the termtest data volume (TDV), or test volume.Test Compression and Compactionis used in conjunction with scan design to reduce the bandwidth and pin count of the interface between CUT and ATE. Test compression reduces the test volume delivered to the CUT. The test set is compressed losslessly, thereby reducing the test volume and the amount of needed tester pins. Additional infrastructure added at the input side of the CUT in form of a decompressor is then used to regenerate the original test set. Test compaction reduces the test volume of the test responses with additional infrastructure, a compactor at the output side of the CUT. It provides a (potentially) lossy compaction of test responses in the space or time domain (or a combination of both). The compacted test responses are then compared with pre-computed responses in the ATE.
1.2.2. Test Economics
Increasing integration densities and raising functionality due to continued scaling have a considerable impact on test cost [ITR13]. Test cost arises from the costs associated with test equipment, the on-chip test infrastructure, and the test application.
The cost for testing a single CUT then depends on the required tester capabilities (e.g.
pin count, speed), the area occupied in the CUT by added test infrastructure, as well as the test time. In addition to testability, secondary metrics play an important role during test as they directly influence the test cost, and thereby the product cost.
Area Overhead.Test infrastructure is added to increase testability, ease test access and reduce the test time and volume. The area overhead associated with test infrastructure is often considered critical in terms of cost, as test infrastructure is often solely used to facilitate testing, but not used during functional operation.
Test Application Time.During volume production, a high amount of ICs is produced in short time. The amount of testers needed to test all ICs during production is determined by the time needed to test a single IC. Thus, test cost scales nearly linear with test time reduction.
Test Data Volume. The amount of test data exchanged with the CUT during test application defines the ATEs minimum memory configuration. As test cost is coupled to the amount as well as the configuration of the required ATEs, test data volume reduction helps towards using adequate ATE configurations with reasonable cost.
Peak and Average Test Power.During test, the power consumption of ICs can be an order of magnitude higher compared to functional operation due to increased switching activity. Thepeak powerdetermines the dimensioning of the circuits power grid. With a raised peak power during test, either the power grid needs to be reinforced and thus overdimensioned beyond normal operation or test quality might be impacted due to voltage droop. The average power is closely related to the thermal design power of an IC. Thus, with a cooling system optimized for functional operation, the heat dissipation during test is limited and elevated temperatures must be compensated by either increasing the test time or by changes in the test architecture.
Test Energy. An average power consumption in excess of the provisioned cooling capabilities can be compensated for short periods of time by exploiting the thermal capacitance of the used materials. Thus, a lowered test energy as the product of test time and average test power enables test conduction under confined cost.